[PATCH] powerpc/44x: Fix address decoding setup of PCI 2.x cells

[PATCH] powerpc/44x: Fix address decoding setup of PCI 2.x cells

[Benjamin Herrenschmidt]

The PCI 2.x cells used on some 44x SoCs only let us configure the decode
for the low 32-bit of the incoming PLB addresses. The top 4 bits (this
is a 36-bit bus) are hard wired to different values depending on the
specific SoC in use. Our code used to work "by accident" until I added
support for the ISA memory holes and while at it added more validity
checking of the addresses.

This patch should bring it back to working condition. It still relies
on the device-tree being correct but that's somewhat a pre-requisite
for anything to work anyway.

Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
---

This is untested. Geert, can you give it a go on Sequoia and let me
know if it fixes your problem ?

 arch/powerpc/sysdev/ppc4xx_pci.c |   17 +++++++++++++++++
 1 file changed, 17 insertions(+)

--- linux-work.orig/arch/powerpc/sysdev/ppc4xx_pci.c	2009-02-02 11:15:35.000000000 +1100
+++ linux-work/arch/powerpc/sysdev/ppc4xx_pci.c	2009-02-02 11:19:03.000000000 +1100
@@ -204,6 +204,23 @@ static int __init ppc4xx_setup_one_pci_P
 {
 	u32 ma, pcila, pciha;
 
+	/* Hack warning ! The "old" PCI 2.x cell only let us configure the low
+	 * 32-bit of incoming PLB addresses. The top 4 bits of the 36-bit
+	 * address are actually hard wired to a value that appears to depend
+	 * on the specific SoC. For example, it's 0 on 440EP and 1 on 440EPx.
+	 *
+	 * The trick here is we just crop those top bits and ignore them when
+	 * programming the chip. That means the device-tree has to be right
+	 * for the specific part used (we don't print a warning if it's wrong
+	 * but on the other hand, you'll crash quickly enough), but at least
+	 * this code should work whatever the hard coded value is
+	 */
+	plb_addr &= 0xffffffffull;
+
+	/* Note: Due to the above hack, the test below doesn't actually test
+	 * if you address is above 4G, but it tests that address and
+	 * (address + size) are both contained in the same 4G
+	 */
 	if ((plb_addr + size) > 0xffffffffull || !is_power_of_2(size) ||
 	    size < 0x1000 || (plb_addr & (size - 1)) != 0) {
 		printk(KERN_WARNING "%s: Resource out of range\n",

Re: [PATCH] powerpc/44x: Fix address decoding setup of PCI 2.x cells

[Geert Uytterhoeven]

On Mon, 2 Feb 2009, Benjamin Herrenschmidt wrote:
> The PCI 2.x cells used on some 44x SoCs only let us configure the decode
> for the low 32-bit of the incoming PLB addresses. The top 4 bits (this
> is a 36-bit bus) are hard wired to different values depending on the
> specific SoC in use. Our code used to work "by accident" until I added
> support for the ISA memory holes and while at it added more validity
> checking of the addresses.
> 
> This patch should bring it back to working condition. It still relies
> on the device-tree being correct but that's somewhat a pre-requisite
> for anything to work anyway.
> 
> Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
> ---
> 
> This is untested. Geert, can you give it a go on Sequoia and let me
> know if it fixes your problem ?

Thanks, it seems to fix the problems.

Acked-by: Geert Uytterhoeven <Geert.Uytterhoeven@sonycom.com>

| sequoia:~# lspci -v
| 00:00.0 Bridge: IBM Device 027f
|         Subsystem: Applied Micro Circuits Corp. Device cafe
|         Flags: bus master, medium devsel, latency 0, IRQ 16
|         Memory at <unassigned> (32-bit, prefetchable)
                    ^^^^^^^^^^^^
Is this expected?

|         Capabilities: [58] Power Management version 2
| 
| 00:0a.0 USB Controller: NEC Corporation USB (rev 43) (prog-if 10 [OHCI])
|         Subsystem: DTK Computer PTI-205N USB 2.0 Host Controller
|         Flags: bus master, medium devsel, latency 8, IRQ 16
|         Memory at 180000000 (32-bit, non-prefetchable) [size=4K]
|         Capabilities: [40] Power Management version 2
|         Kernel driver in use: ohci_hcd
| 
| 00:0a.1 USB Controller: NEC Corporation USB (rev 43) (prog-if 10 [OHCI])
|         Subsystem: DTK Computer PTI-205N USB 2.0 Host Controller
|         Flags: bus master, medium devsel, latency 8, IRQ 16
|         Memory at 180001000 (32-bit, non-prefetchable) [size=4K]
|         Capabilities: [40] Power Management version 2
|         Kernel driver in use: ohci_hcd
| 
| 00:0a.2 USB Controller: NEC Corporation USB 2.0 (rev 04) (prog-if 20 [EHCI])
|         Subsystem: DTK Computer PTI-205N USB 2.0 Host Controller
|         Flags: bus master, medium devsel, latency 68, IRQ 16
|         Memory at 180002000 (32-bit, non-prefetchable) [size=256]
|         Capabilities: [40] Power Management version 2
|         Kernel driver in use: ehci_hcd
| 
| sequoia:~# 

However, 'lsusb' doesn't detect any USB devices connected to the USB PCI card, except for
the root hubs:

| sequoia:~# lsusb
| Bus 003 Device 001: ID 1d6b:0001 Linux Foundation 1.1 root hub
| Bus 002 Device 001: ID 1d6b:0001 Linux Foundation 1.1 root hub
| Bus 001 Device 001: ID 1d6b:0002 Linux Foundation 2.0 root hub
| sequoia:~# 

An E1000 Ethernet card does work fine now.

With kind regards,

Geert Uytterhoeven
Software Architect

Sony Techsoft Centre Europe
The Corporate Village · Da Vincilaan 7-D1 · B-1935 Zaventem · Belgium

Phone:    +32 (0)2 700 8453
Fax:      +32 (0)2 700 8622
E-mail:   Geert.Uytterhoeven@sonycom.com
Internet: http://www.sony-europe.com/

A division of Sony Europe (Belgium) N.V.
VAT BE 0413.825.160 · RPR Brussels
Fortis · BIC GEBABEBB · IBAN BE41293037680010

Re: [PATCH] powerpc/44x: Fix address decoding setup of PCI 2.x cells

[Josh Boyer]

On Mon, Feb 02, 2009 at 11:24:18AM +1100, Benjamin Herrenschmidt wrote:
>The PCI 2.x cells used on some 44x SoCs only let us configure the decode
>for the low 32-bit of the incoming PLB addresses. The top 4 bits (this
>is a 36-bit bus) are hard wired to different values depending on the
>specific SoC in use. Our code used to work "by accident" until I added
>support for the ISA memory holes and while at it added more validity
>checking of the addresses.
>
>This patch should bring it back to working condition. It still relies
>on the device-tree being correct but that's somewhat a pre-requisite
>for anything to work anyway.
>
>Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
>---
>
>This is untested. Geert, can you give it a go on Sequoia and let me
>know if it fixes your problem ?

Since Geert tested it somewhat successfully, perhaps we should get
this one into 2.6.29.  I have no other fixes outstanding, so feel
free to pull it in yourself.

Acked-by: Josh Boyer <jwboyer@linux.vnet.ibm.com>

josh

Re: [PATCH] powerpc/44x: Fix address decoding setup of PCI 2.x cells

[Geert Uytterhoeven]

On Tue, 3 Feb 2009, Josh Boyer wrote:
> On Mon, Feb 02, 2009 at 11:24:18AM +1100, Benjamin Herrenschmidt wrote:
> >The PCI 2.x cells used on some 44x SoCs only let us configure the decode
> >for the low 32-bit of the incoming PLB addresses. The top 4 bits (this
> >is a 36-bit bus) are hard wired to different values depending on the
> >specific SoC in use. Our code used to work "by accident" until I added
> >support for the ISA memory holes and while at it added more validity
> >checking of the addresses.
> >
> >This patch should bring it back to working condition. It still relies
> >on the device-tree being correct but that's somewhat a pre-requisite
> >for anything to work anyway.
> >
> >Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
> >---
> >
> >This is untested. Geert, can you give it a go on Sequoia and let me
> >know if it fixes your problem ?
> 
> Since Geert tested it somewhat successfully, perhaps we should get
> this one into 2.6.29.  I have no other fixes outstanding, so feel
> free to pull it in yourself.

Could it be my USB failures were due to the PPC440 USB host needing the various
CONFIG*USB*BIG_ENDIAN* options, which may conflict with USB hosts on PCI
plug-in cards?

The E1000 did work fine.

With kind regards,

Geert Uytterhoeven
Software Architect

Sony Techsoft Centre Europe
The Corporate Village · Da Vincilaan 7-D1 · B-1935 Zaventem · Belgium

Phone:    +32 (0)2 700 8453
Fax:      +32 (0)2 700 8622
E-mail:   Geert.Uytterhoeven@sonycom.com
Internet: http://www.sony-europe.com/

A division of Sony Europe (Belgium) N.V.
VAT BE 0413.825.160 · RPR Brussels
Fortis · BIC GEBABEBB · IBAN BE41293037680010

Re: [PATCH] powerpc/44x: Fix address decoding setup of PCI 2.x cells

[Benjamin Herrenschmidt]

> Could it be my USB failures were due to the PPC440 USB host needing the various
> CONFIG*USB*BIG_ENDIAN* options, which may conflict with USB hosts on PCI
> plug-in cards?
> 
> The E1000 did work fine.

You need to enable support for both endians, that's supposed to work.

Ben.

Re: [PATCH] powerpc/44x: Fix address decoding setup of PCI 2.x cells

[Geert Uytterhoeven]

On Tue, 3 Feb 2009, Josh Boyer wrote:
> On Mon, Feb 02, 2009 at 11:24:18AM +1100, Benjamin Herrenschmidt wrote:
> >The PCI 2.x cells used on some 44x SoCs only let us configure the decode
> >for the low 32-bit of the incoming PLB addresses. The top 4 bits (this
> >is a 36-bit bus) are hard wired to different values depending on the
> >specific SoC in use. Our code used to work "by accident" until I added
> >support for the ISA memory holes and while at it added more validity
> >checking of the addresses.
> >
> >This patch should bring it back to working condition. It still relies
> >on the device-tree being correct but that's somewhat a pre-requisite
> >for anything to work anyway.
> >
> >Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
> >---
> >
> >This is untested. Geert, can you give it a go on Sequoia and let me
> >know if it fixes your problem ?
> 
> Since Geert tested it somewhat successfully, perhaps we should get
> this one into 2.6.29.  I have no other fixes outstanding, so feel
> free to pull it in yourself.
> 
> Acked-by: Josh Boyer <jwboyer@linux.vnet.ibm.com>

Indeed, can we please get it in 2.6.29?

(I know you wanted the original breakage into 2.6.28 as a last minute "fix" ---
 fortunately that didn't happen ---, but that doesn't mean we shouldn't fix
 the breakage for 2.6.29 :-)

With kind regards,

Geert Uytterhoeven
Software Architect

Sony Techsoft Centre Europe
The Corporate Village · Da Vincilaan 7-D1 · B-1935 Zaventem · Belgium

Phone:    +32 (0)2 700 8453
Fax:      +32 (0)2 700 8622
E-mail:   Geert.Uytterhoeven@sonycom.com
Internet: http://www.sony-europe.com/

A division of Sony Europe (Belgium) N.V.
VAT BE 0413.825.160 · RPR Brussels
Fortis · BIC GEBABEBB · IBAN BE41293037680010