SPI-Difference between MX1 and MX31

[Wolfram Sang <w.sang@pengutronix.de>]

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Hello,

while working on a generic SPI-driver for the i.MX-platform I stumbled
over the following:

The MX1 can flush its FIFOs using the enable bit. Documentation says:

"SPI Module Enable - Enables/Disables the serial peripheral interface.
SPIEN must be asserted before an exchange is initiated. Writing 0 to
SPIEN flushes the receive and transmit FIFOs."

Furthermore it has a dedicated reset register:

"Start - Executes soft reset."

However, the MX31 does not have a reset register and the documentation
says this regarding the enable bit:

"SPI Module Enable Control - This bit enables the CSPI. This bit must be
asserted before writing to other registers or initiating an exchange.
Writing zero to this bit disables the module and resets the internal
logic with the exception of the CONREG. The module’s internal clocks are
gated off whenever the module is disabled."

So, as I read all this, disabling the enable bit on the MX31 is more
like a soft reset on MX1, right? And there does not seem to be a way to
flush the FIFOs. Can someone imagine what problems might arise if there
is no way to flush the FIFOs? At least, the check for XCH should have
ensured that the TXFIFO is empty...

Looking forward to feedback :)

Regards,

   Wolfram Sang

-- 
Pengutronix e.K.                           | Wolfram Sang                |
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