* [PATCH 2/2] powerpc/83xx: Fix TSEC0 workability on MPC8313E-RDB boards @ 2009-02-05 20:10 Anton Vorontsov 2009-02-06 16:39 ` Kumar Gala 2009-02-09 7:47 ` Li Yang 0 siblings, 2 replies; 13+ messages in thread From: Anton Vorontsov @ 2009-02-05 20:10 UTC (permalink / raw) To: Kumar Gala; +Cc: linuxppc-dev TSEC0 is connected to Vitesse 7385 5-port switch. The switch isn't connected to any mdio bus, the link to the switch is fixed to Full-duplex 1000 Mb/s (no pause). This patch fixes following failure during bootup: mdio@24520:01 not found eth0: Could not attach to PHY IP-Config: Failed to open eth0 Signed-off-by: Anton Vorontsov <avorontsov@ru.mvista.com> --- arch/powerpc/boot/dts/mpc8313erdb.dts | 9 ++------- arch/powerpc/configs/83xx/mpc8313_rdb_defconfig | 2 +- 2 files changed, 3 insertions(+), 8 deletions(-) diff --git a/arch/powerpc/boot/dts/mpc8313erdb.dts b/arch/powerpc/boot/dts/mpc8313erdb.dts index 3f84cd0..3ebf7ec 100644 --- a/arch/powerpc/boot/dts/mpc8313erdb.dts +++ b/arch/powerpc/boot/dts/mpc8313erdb.dts @@ -191,7 +191,8 @@ interrupts = <37 0x8 36 0x8 35 0x8>; interrupt-parent = <&ipic>; tbi-handle = < &tbi0 >; - phy-handle = < &phy1 >; + /* Vitesse 7385 isn't on the MDIO bus */ + fixed-link = <1 1 1000 0 0>; fsl,magic-packet; mdio@24520 { @@ -199,12 +200,6 @@ #size-cells = <0>; compatible = "fsl,gianfar-mdio"; reg = <0x24520 0x20>; - phy1: ethernet-phy@1 { - interrupt-parent = <&ipic>; - interrupts = <19 0x8>; - reg = <0x1>; - device_type = "ethernet-phy"; - }; phy4: ethernet-phy@4 { interrupt-parent = <&ipic>; interrupts = <20 0x8>; diff --git a/arch/powerpc/configs/83xx/mpc8313_rdb_defconfig b/arch/powerpc/configs/83xx/mpc8313_rdb_defconfig index 9e47ae9..409d017 100644 --- a/arch/powerpc/configs/83xx/mpc8313_rdb_defconfig +++ b/arch/powerpc/configs/83xx/mpc8313_rdb_defconfig @@ -651,7 +651,7 @@ CONFIG_CICADA_PHY=y # CONFIG_NATIONAL_PHY is not set # CONFIG_STE10XP is not set # CONFIG_LSI_ET1011C_PHY is not set -# CONFIG_FIXED_PHY is not set +CONFIG_FIXED_PHY=y # CONFIG_MDIO_BITBANG is not set CONFIG_NET_ETHERNET=y CONFIG_MII=y -- 1.5.6.5 ^ permalink raw reply related [flat|nested] 13+ messages in thread
* Re: [PATCH 2/2] powerpc/83xx: Fix TSEC0 workability on MPC8313E-RDB boards 2009-02-05 20:10 [PATCH 2/2] powerpc/83xx: Fix TSEC0 workability on MPC8313E-RDB boards Anton Vorontsov @ 2009-02-06 16:39 ` Kumar Gala 2009-02-09 7:47 ` Li Yang 1 sibling, 0 replies; 13+ messages in thread From: Kumar Gala @ 2009-02-06 16:39 UTC (permalink / raw) To: Anton Vorontsov; +Cc: linuxppc-dev On Feb 5, 2009, at 2:10 PM, Anton Vorontsov wrote: > TSEC0 is connected to Vitesse 7385 5-port switch. The switch > isn't connected to any mdio bus, the link to the switch is fixed > to Full-duplex 1000 Mb/s (no pause). > > This patch fixes following failure during bootup: > > mdio@24520:01 not found > eth0: Could not attach to PHY > IP-Config: Failed to open eth0 > > Signed-off-by: Anton Vorontsov <avorontsov@ru.mvista.com> > --- > arch/powerpc/boot/dts/mpc8313erdb.dts | 9 ++------- > arch/powerpc/configs/83xx/mpc8313_rdb_defconfig | 2 +- > 2 files changed, 3 insertions(+), 8 deletions(-) applied to merge - k ^ permalink raw reply [flat|nested] 13+ messages in thread
* Re: [PATCH 2/2] powerpc/83xx: Fix TSEC0 workability on MPC8313E-RDB boards 2009-02-05 20:10 [PATCH 2/2] powerpc/83xx: Fix TSEC0 workability on MPC8313E-RDB boards Anton Vorontsov 2009-02-06 16:39 ` Kumar Gala @ 2009-02-09 7:47 ` Li Yang 2009-02-09 15:32 ` Kumar Gala 1 sibling, 1 reply; 13+ messages in thread From: Li Yang @ 2009-02-09 7:47 UTC (permalink / raw) To: Anton Vorontsov; +Cc: linuxppc-dev On Fri, Feb 6, 2009 at 4:10 AM, Anton Vorontsov <avorontsov@ru.mvista.com> wrote: > TSEC0 is connected to Vitesse 7385 5-port switch. The switch > isn't connected to any mdio bus, the link to the switch is fixed > to Full-duplex 1000 Mb/s (no pause). It's a complex case for RDB boards. The revision A and revision B boards DO always connect TSEC0 to Vitesse switch. While the latest revision C board has one setting to connect TSEC0 to a Marvell PHY and MDIO bus. In BSP we have several DTS's for each setting of the board, shouldn't we do the same for upstream? - Leo ^ permalink raw reply [flat|nested] 13+ messages in thread
* Re: [PATCH 2/2] powerpc/83xx: Fix TSEC0 workability on MPC8313E-RDB boards 2009-02-09 7:47 ` Li Yang @ 2009-02-09 15:32 ` Kumar Gala 2009-02-10 15:10 ` [PATCH] powerpc/83xx: Revive Marvell PHY option on MPC8313E-RDB rev. C boards Anton Vorontsov 0 siblings, 1 reply; 13+ messages in thread From: Kumar Gala @ 2009-02-09 15:32 UTC (permalink / raw) To: Li Yang; +Cc: linuxppc-dev On Feb 9, 2009, at 1:47 AM, Li Yang wrote: > > It's a complex case for RDB boards. The revision A and revision B > boards DO always connect TSEC0 to Vitesse switch. While the latest > revision C board has one setting to connect TSEC0 to a Marvell PHY and > MDIO bus. In BSP we have several DTS's for each setting of the board, > shouldn't we do the same for upstream? Is this something we can detect and deal with in u-boot? If not than having multiple .dts for the revisions seems like the only solution. - k ^ permalink raw reply [flat|nested] 13+ messages in thread
* [PATCH] powerpc/83xx: Revive Marvell PHY option on MPC8313E-RDB rev. C boards 2009-02-09 15:32 ` Kumar Gala @ 2009-02-10 15:10 ` Anton Vorontsov 2009-02-10 15:30 ` Kumar Gala 2009-02-12 5:24 ` Kumar Gala 0 siblings, 2 replies; 13+ messages in thread From: Anton Vorontsov @ 2009-02-10 15:10 UTC (permalink / raw) To: Kumar Gala; +Cc: linuxppc-dev, Li Yang commit e85477f516c2de7ed515fcf94ceab5282eba7fa4 ("powerpc/83xx: Fix TSEC0 workability on MPC8313E-RDB boards") fixed TSEC0 workability for rev. A and rev. B boards by using fixed-link property for VSC 7385 5-port switch. But rev. C boards have an option where TSEC0 connected to a Marvell PHY, which is a normal PHY on MDIO bus. So far U-Boot does not fix up TSEC0 nodes for MPC8313E-RDB boards, so we'd better include two device-tree files: one that specify Vitesse PHY and another for boards with Marvell PHY option. Reported-by: Li Yang <leoli@freescale.com> Signed-off-by: Anton Vorontsov <avorontsov@ru.mvista.com> --- Li, thanks for heads-up! One thing though: documentation says that Marvell PHY address is 0x3, while old device tree and this patch: http://www.bitshrine.org/gpp/linux-fsl-2.6.23-MPC8313ERDB-add-default-dts.patch says "0x1"... I don't have any rev. C boards, so it would be great if somebody could confirm that 0x1 is the actual address. arch/powerpc/boot/dts/mpc8313erdb_marvell_phy.dts | 401 +++++++++++++++++++++ arch/powerpc/configs/83xx/mpc8313_rdb_defconfig | 2 +- 2 files changed, 402 insertions(+), 1 deletions(-) create mode 100644 arch/powerpc/boot/dts/mpc8313erdb_marvell_phy.dts diff --git a/arch/powerpc/boot/dts/mpc8313erdb_marvell_phy.dts b/arch/powerpc/boot/dts/mpc8313erdb_marvell_phy.dts new file mode 100644 index 0000000..3f84cd0 --- /dev/null +++ b/arch/powerpc/boot/dts/mpc8313erdb_marvell_phy.dts @@ -0,0 +1,401 @@ +/* + * MPC8313E RDB Device Tree Source + * + * Copyright 2005, 2006, 2007 Freescale Semiconductor Inc. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License as published by the + * Free Software Foundation; either version 2 of the License, or (at your + * option) any later version. + */ + +/dts-v1/; + +/ { + model = "MPC8313ERDB"; + compatible = "MPC8313ERDB", "MPC831xRDB", "MPC83xxRDB"; + #address-cells = <1>; + #size-cells = <1>; + + aliases { + ethernet0 = &enet0; + ethernet1 = &enet1; + serial0 = &serial0; + serial1 = &serial1; + pci0 = &pci0; + }; + + cpus { + #address-cells = <1>; + #size-cells = <0>; + + PowerPC,8313@0 { + device_type = "cpu"; + reg = <0x0>; + d-cache-line-size = <32>; + i-cache-line-size = <32>; + d-cache-size = <16384>; + i-cache-size = <16384>; + timebase-frequency = <0>; // from bootloader + bus-frequency = <0>; // from bootloader + clock-frequency = <0>; // from bootloader + }; + }; + + memory { + device_type = "memory"; + reg = <0x00000000 0x08000000>; // 128MB at 0 + }; + + localbus@e0005000 { + #address-cells = <2>; + #size-cells = <1>; + compatible = "fsl,mpc8313-elbc", "fsl,elbc", "simple-bus"; + reg = <0xe0005000 0x1000>; + interrupts = <77 0x8>; + interrupt-parent = <&ipic>; + + // CS0 and CS1 are swapped when + // booting from nand, but the + // addresses are the same. + ranges = <0x0 0x0 0xfe000000 0x00800000 + 0x1 0x0 0xe2800000 0x00008000 + 0x2 0x0 0xf0000000 0x00020000 + 0x3 0x0 0xfa000000 0x00008000>; + + flash@0,0 { + #address-cells = <1>; + #size-cells = <1>; + compatible = "cfi-flash"; + reg = <0x0 0x0 0x800000>; + bank-width = <2>; + device-width = <1>; + }; + + nand@1,0 { + #address-cells = <1>; + #size-cells = <1>; + compatible = "fsl,mpc8313-fcm-nand", + "fsl,elbc-fcm-nand"; + reg = <0x1 0x0 0x2000>; + + u-boot@0 { + reg = <0x0 0x100000>; + read-only; + }; + + kernel@100000 { + reg = <0x100000 0x300000>; + }; + + fs@400000 { + reg = <0x400000 0x1c00000>; + }; + }; + }; + + soc8313@e0000000 { + #address-cells = <1>; + #size-cells = <1>; + device_type = "soc"; + compatible = "simple-bus"; + ranges = <0x0 0xe0000000 0x00100000>; + reg = <0xe0000000 0x00000200>; + bus-frequency = <0>; + + wdt@200 { + device_type = "watchdog"; + compatible = "mpc83xx_wdt"; + reg = <0x200 0x100>; + }; + + sleep-nexus { + #address-cells = <1>; + #size-cells = <1>; + compatible = "simple-bus"; + sleep = <&pmc 0x03000000>; + ranges; + + i2c@3000 { + #address-cells = <1>; + #size-cells = <0>; + cell-index = <0>; + compatible = "fsl-i2c"; + reg = <0x3000 0x100>; + interrupts = <14 0x8>; + interrupt-parent = <&ipic>; + dfsrr; + rtc@68 { + compatible = "dallas,ds1339"; + reg = <0x68>; + }; + }; + + crypto@30000 { + compatible = "fsl,sec2.2", "fsl,sec2.1", + "fsl,sec2.0"; + reg = <0x30000 0x10000>; + interrupts = <11 0x8>; + interrupt-parent = <&ipic>; + fsl,num-channels = <1>; + fsl,channel-fifo-len = <24>; + fsl,exec-units-mask = <0x4c>; + fsl,descriptor-types-mask = <0x0122003f>; + }; + }; + + i2c@3100 { + #address-cells = <1>; + #size-cells = <0>; + cell-index = <1>; + compatible = "fsl-i2c"; + reg = <0x3100 0x100>; + interrupts = <15 0x8>; + interrupt-parent = <&ipic>; + dfsrr; + }; + + spi@7000 { + cell-index = <0>; + compatible = "fsl,spi"; + reg = <0x7000 0x1000>; + interrupts = <16 0x8>; + interrupt-parent = <&ipic>; + mode = "cpu"; + }; + + /* phy type (ULPI, UTMI, UTMI_WIDE, SERIAL) */ + usb@23000 { + compatible = "fsl-usb2-dr"; + reg = <0x23000 0x1000>; + #address-cells = <1>; + #size-cells = <0>; + interrupt-parent = <&ipic>; + interrupts = <38 0x8>; + phy_type = "utmi_wide"; + sleep = <&pmc 0x00300000>; + }; + + enet0: ethernet@24000 { + #address-cells = <1>; + #size-cells = <1>; + sleep = <&pmc 0x20000000>; + ranges; + + cell-index = <0>; + device_type = "network"; + model = "eTSEC"; + compatible = "gianfar"; + reg = <0x24000 0x1000>; + local-mac-address = [ 00 00 00 00 00 00 ]; + interrupts = <37 0x8 36 0x8 35 0x8>; + interrupt-parent = <&ipic>; + tbi-handle = < &tbi0 >; + phy-handle = < &phy1 >; + fsl,magic-packet; + + mdio@24520 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "fsl,gianfar-mdio"; + reg = <0x24520 0x20>; + phy1: ethernet-phy@1 { + interrupt-parent = <&ipic>; + interrupts = <19 0x8>; + reg = <0x1>; + device_type = "ethernet-phy"; + }; + phy4: ethernet-phy@4 { + interrupt-parent = <&ipic>; + interrupts = <20 0x8>; + reg = <0x4>; + device_type = "ethernet-phy"; + }; + tbi0: tbi-phy@11 { + reg = <0x11>; + device_type = "tbi-phy"; + }; + }; + }; + + enet1: ethernet@25000 { + #address-cells = <1>; + #size-cells = <1>; + cell-index = <1>; + device_type = "network"; + model = "eTSEC"; + compatible = "gianfar"; + reg = <0x25000 0x1000>; + local-mac-address = [ 00 00 00 00 00 00 ]; + interrupts = <34 0x8 33 0x8 32 0x8>; + interrupt-parent = <&ipic>; + tbi-handle = < &tbi1 >; + phy-handle = < &phy4 >; + sleep = <&pmc 0x10000000>; + fsl,magic-packet; + + mdio@25520 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "fsl,gianfar-tbi"; + reg = <0x25520 0x20>; + + tbi1: tbi-phy@11 { + reg = <0x11>; + device_type = "tbi-phy"; + }; + }; + + + }; + + serial0: serial@4500 { + cell-index = <0>; + device_type = "serial"; + compatible = "ns16550"; + reg = <0x4500 0x100>; + clock-frequency = <0>; + interrupts = <9 0x8>; + interrupt-parent = <&ipic>; + }; + + serial1: serial@4600 { + cell-index = <1>; + device_type = "serial"; + compatible = "ns16550"; + reg = <0x4600 0x100>; + clock-frequency = <0>; + interrupts = <10 0x8>; + interrupt-parent = <&ipic>; + }; + + /* IPIC + * interrupts cell = <intr #, sense> + * sense values match linux IORESOURCE_IRQ_* defines: + * sense == 8: Level, low assertion + * sense == 2: Edge, high-to-low change + */ + ipic: pic@700 { + interrupt-controller; + #address-cells = <0>; + #interrupt-cells = <2>; + reg = <0x700 0x100>; + device_type = "ipic"; + }; + + pmc: power@b00 { + compatible = "fsl,mpc8313-pmc", "fsl,mpc8349-pmc"; + reg = <0xb00 0x100 0xa00 0x100>; + interrupts = <80 8>; + interrupt-parent = <&ipic>; + fsl,mpc8313-wakeup-timer = <>m1>; + + /* Remove this (or change to "okay") if you have + * a REVA3 or later board, if you apply one of the + * workarounds listed in section 8.5 of the board + * manual, or if you are adapting this device tree + * to a different board. + */ + status = "fail"; + }; + + gtm1: timer@500 { + compatible = "fsl,mpc8313-gtm", "fsl,gtm"; + reg = <0x500 0x100>; + interrupts = <90 8 78 8 84 8 72 8>; + interrupt-parent = <&ipic>; + }; + + timer@600 { + compatible = "fsl,mpc8313-gtm", "fsl,gtm"; + reg = <0x600 0x100>; + interrupts = <91 8 79 8 85 8 73 8>; + interrupt-parent = <&ipic>; + }; + }; + + sleep-nexus { + #address-cells = <1>; + #size-cells = <1>; + compatible = "simple-bus"; + sleep = <&pmc 0x00010000>; + ranges; + + pci0: pci@e0008500 { + cell-index = <1>; + interrupt-map-mask = <0xf800 0x0 0x0 0x7>; + interrupt-map = < + /* IDSEL 0x0E -mini PCI */ + 0x7000 0x0 0x0 0x1 &ipic 18 0x8 + 0x7000 0x0 0x0 0x2 &ipic 18 0x8 + 0x7000 0x0 0x0 0x3 &ipic 18 0x8 + 0x7000 0x0 0x0 0x4 &ipic 18 0x8 + + /* IDSEL 0x0F - PCI slot */ + 0x7800 0x0 0x0 0x1 &ipic 17 0x8 + 0x7800 0x0 0x0 0x2 &ipic 18 0x8 + 0x7800 0x0 0x0 0x3 &ipic 17 0x8 + 0x7800 0x0 0x0 0x4 &ipic 18 0x8>; + interrupt-parent = <&ipic>; + interrupts = <66 0x8>; + bus-range = <0x0 0x0>; + ranges = <0x02000000 0x0 0x90000000 0x90000000 0x0 0x10000000 + 0x42000000 0x0 0x80000000 0x80000000 0x0 0x10000000 + 0x01000000 0x0 0x00000000 0xe2000000 0x0 0x00100000>; + clock-frequency = <66666666>; + #interrupt-cells = <1>; + #size-cells = <2>; + #address-cells = <3>; + reg = <0xe0008500 0x100 /* internal registers */ + 0xe0008300 0x8>; /* config space access registers */ + compatible = "fsl,mpc8349-pci"; + device_type = "pci"; + }; + + dma@82a8 { + #address-cells = <1>; + #size-cells = <1>; + compatible = "fsl,mpc8313-dma", "fsl,elo-dma"; + reg = <0xe00082a8 4>; + ranges = <0 0xe0008100 0x1a8>; + interrupt-parent = <&ipic>; + interrupts = <71 8>; + + dma-channel@0 { + compatible = "fsl,mpc8313-dma-channel", + "fsl,elo-dma-channel"; + reg = <0 0x28>; + interrupt-parent = <&ipic>; + interrupts = <71 8>; + cell-index = <0>; + }; + + dma-channel@80 { + compatible = "fsl,mpc8313-dma-channel", + "fsl,elo-dma-channel"; + reg = <0x80 0x28>; + interrupt-parent = <&ipic>; + interrupts = <71 8>; + cell-index = <1>; + }; + + dma-channel@100 { + compatible = "fsl,mpc8313-dma-channel", + "fsl,elo-dma-channel"; + reg = <0x100 0x28>; + interrupt-parent = <&ipic>; + interrupts = <71 8>; + cell-index = <2>; + }; + + dma-channel@180 { + compatible = "fsl,mpc8313-dma-channel", + "fsl,elo-dma-channel"; + reg = <0x180 0x28>; + interrupt-parent = <&ipic>; + interrupts = <71 8>; + cell-index = <3>; + }; + }; + }; +}; diff --git a/arch/powerpc/configs/83xx/mpc8313_rdb_defconfig b/arch/powerpc/configs/83xx/mpc8313_rdb_defconfig index 409d017..cf908af 100644 --- a/arch/powerpc/configs/83xx/mpc8313_rdb_defconfig +++ b/arch/powerpc/configs/83xx/mpc8313_rdb_defconfig @@ -638,7 +638,7 @@ CONFIG_PHYLIB=y # # MII PHY device drivers # -# CONFIG_MARVELL_PHY is not set +CONFIG_MARVELL_PHY=y # CONFIG_DAVICOM_PHY is not set # CONFIG_QSEMI_PHY is not set # CONFIG_LXT_PHY is not set -- 1.5.6.5 ^ permalink raw reply related [flat|nested] 13+ messages in thread
* Re: [PATCH] powerpc/83xx: Revive Marvell PHY option on MPC8313E-RDB rev. C boards 2009-02-10 15:10 ` [PATCH] powerpc/83xx: Revive Marvell PHY option on MPC8313E-RDB rev. C boards Anton Vorontsov @ 2009-02-10 15:30 ` Kumar Gala 2009-02-12 2:36 ` Li Yang-R58472 2009-02-12 5:24 ` Kumar Gala 1 sibling, 1 reply; 13+ messages in thread From: Kumar Gala @ 2009-02-10 15:30 UTC (permalink / raw) To: avorontsov; +Cc: linuxppc-dev, Li Yang On Feb 10, 2009, at 9:10 AM, Anton Vorontsov wrote: > commit e85477f516c2de7ed515fcf94ceab5282eba7fa4 ("powerpc/83xx: Fix > TSEC0 workability on MPC8313E-RDB boards") fixed TSEC0 workability for > rev. A and rev. B boards by using fixed-link property for VSC 7385 > 5-port switch. But rev. C boards have an option where TSEC0 connected > to a Marvell PHY, which is a normal PHY on MDIO bus. > > So far U-Boot does not fix up TSEC0 nodes for MPC8313E-RDB boards, so > we'd better include two device-tree files: one that specify Vitesse > PHY and another for boards with Marvell PHY option. > > Reported-by: Li Yang <leoli@freescale.com> > Signed-off-by: Anton Vorontsov <avorontsov@ru.mvista.com> > --- > > Li, thanks for heads-up! > > One thing though: documentation says that Marvell PHY address is > 0x3, while old device tree and this patch: > > http://www.bitshrine.org/gpp/linux-fsl-2.6.23-MPC8313ERDB-add-default-dts.patch > > says "0x1"... I don't have any rev. C boards, so it would > be great if somebody could confirm that 0x1 is the actual address. > > arch/powerpc/boot/dts/mpc8313erdb_marvell_phy.dts | 401 ++++++++++++ > +++++++++ > arch/powerpc/configs/83xx/mpc8313_rdb_defconfig | 2 +- > 2 files changed, 402 insertions(+), 1 deletions(-) > create mode 100644 arch/powerpc/boot/dts/mpc8313erdb_marvell_phy.dts did we decide that we don't have any bcsr or something that convey board rev or this setting? - k ^ permalink raw reply [flat|nested] 13+ messages in thread
* RE: [PATCH] powerpc/83xx: Revive Marvell PHY option on MPC8313E-RDB rev. C boards 2009-02-10 15:30 ` Kumar Gala @ 2009-02-12 2:36 ` Li Yang-R58472 2009-02-12 5:25 ` Kumar Gala 0 siblings, 1 reply; 13+ messages in thread From: Li Yang-R58472 @ 2009-02-12 2:36 UTC (permalink / raw) To: Kumar Gala, avorontsov; +Cc: linuxppc-dev > -----Original Message----- > From: Kumar Gala [mailto:galak@kernel.crashing.org]=20 > Sent: Tuesday, February 10, 2009 11:31 PM > To: avorontsov@ru.mvista.com > Cc: Li Yang-R58472; linuxppc-dev@ozlabs.org > Subject: Re: [PATCH] powerpc/83xx: Revive Marvell PHY option=20 > on MPC8313E-RDB rev. C boards >=20 >=20 > On Feb 10, 2009, at 9:10 AM, Anton Vorontsov wrote: >=20 > > commit e85477f516c2de7ed515fcf94ceab5282eba7fa4 ("powerpc/83xx: Fix=20 > > TSEC0 workability on MPC8313E-RDB boards") fixed TSEC0=20 > workability for=20 > > rev. A and rev. B boards by using fixed-link property for VSC 7385=20 > > 5-port switch. But rev. C boards have an option where TSEC0=20 > connected=20 > > to a Marvell PHY, which is a normal PHY on MDIO bus. > > > > So far U-Boot does not fix up TSEC0 nodes for MPC8313E-RDB=20 > boards, so=20 > > we'd better include two device-tree files: one that specify Vitesse=20 > > PHY and another for boards with Marvell PHY option. > > > > Reported-by: Li Yang <leoli@freescale.com> > > Signed-off-by: Anton Vorontsov <avorontsov@ru.mvista.com> > > --- > > > > Li, thanks for heads-up! > > > > One thing though: documentation says that Marvell PHY=20 > address is 0x3,=20 > > while old device tree and this patch: > > > >=20 > http://www.bitshrine.org/gpp/linux-fsl-2.6.23-MPC8313ERDB-add-default- > > dts.patch > > > > says "0x1"... I don't have any rev. C boards, so it would=20 > be great if=20 > > somebody could confirm that 0x1 is the actual address. > > > > arch/powerpc/boot/dts/mpc8313erdb_marvell_phy.dts | 401=20 > ++++++++++++ > > +++++++++ > > arch/powerpc/configs/83xx/mpc8313_rdb_defconfig | 2 +- > > 2 files changed, 402 insertions(+), 1 deletions(-) create=20 > mode 100644=20 > > arch/powerpc/boot/dts/mpc8313erdb_marvell_phy.dts >=20 > did we decide that we don't have any bcsr or something that=20 > convey board rev or this setting? Nope for now. The board do have two revision bits readable to the core, one bit set by resisters and the other set by a switch. We don't currently have a convention for using these two bits. And apperently they can't cover the information of both the board revision and setup. - Leo ^ permalink raw reply [flat|nested] 13+ messages in thread
* Re: [PATCH] powerpc/83xx: Revive Marvell PHY option on MPC8313E-RDB rev. C boards 2009-02-12 2:36 ` Li Yang-R58472 @ 2009-02-12 5:25 ` Kumar Gala 0 siblings, 0 replies; 13+ messages in thread From: Kumar Gala @ 2009-02-12 5:25 UTC (permalink / raw) To: Li Yang-R58472; +Cc: linuxppc-dev >> On Feb 10, 2009, at 9:10 AM, Anton Vorontsov wrote: >> >>> commit e85477f516c2de7ed515fcf94ceab5282eba7fa4 ("powerpc/83xx: Fix >>> TSEC0 workability on MPC8313E-RDB boards") fixed TSEC0 >> workability for >>> rev. A and rev. B boards by using fixed-link property for VSC 7385 >>> 5-port switch. But rev. C boards have an option where TSEC0 >> connected >>> to a Marvell PHY, which is a normal PHY on MDIO bus. >>> >>> So far U-Boot does not fix up TSEC0 nodes for MPC8313E-RDB >> boards, so >>> we'd better include two device-tree files: one that specify Vitesse >>> PHY and another for boards with Marvell PHY option. >>> >>> Reported-by: Li Yang <leoli@freescale.com> >>> Signed-off-by: Anton Vorontsov <avorontsov@ru.mvista.com> >>> --- >>> >>> Li, thanks for heads-up! >>> >>> One thing though: documentation says that Marvell PHY >> address is 0x3, >>> while old device tree and this patch: >>> >>> >> http://www.bitshrine.org/gpp/linux-fsl-2.6.23-MPC8313ERDB-add- >> default- >>> dts.patch >>> >>> says "0x1"... I don't have any rev. C boards, so it would >> be great if >>> somebody could confirm that 0x1 is the actual address. >>> >>> arch/powerpc/boot/dts/mpc8313erdb_marvell_phy.dts | 401 >> ++++++++++++ >>> +++++++++ >>> arch/powerpc/configs/83xx/mpc8313_rdb_defconfig | 2 +- >>> 2 files changed, 402 insertions(+), 1 deletions(-) create >> mode 100644 >>> arch/powerpc/boot/dts/mpc8313erdb_marvell_phy.dts >> >> did we decide that we don't have any bcsr or something that >> convey board rev or this setting? > > Nope for now. The board do have two revision bits readable to the > core, > one bit set by resisters and the other set by a switch. We don't > currently have a convention for using these two bits. And apperently > they can't cover the information of both the board revision and setup. > > - Leo ok. I'll take the patch pending the other question Anton raised about the phy id. - k ^ permalink raw reply [flat|nested] 13+ messages in thread
* Re: [PATCH] powerpc/83xx: Revive Marvell PHY option on MPC8313E-RDB rev. C boards 2009-02-10 15:10 ` [PATCH] powerpc/83xx: Revive Marvell PHY option on MPC8313E-RDB rev. C boards Anton Vorontsov 2009-02-10 15:30 ` Kumar Gala @ 2009-02-12 5:24 ` Kumar Gala 2009-02-12 5:40 ` Li Yang-R58472 1 sibling, 1 reply; 13+ messages in thread From: Kumar Gala @ 2009-02-12 5:24 UTC (permalink / raw) To: Li Yang; +Cc: linuxppc-dev list On Feb 10, 2009, at 9:10 AM, Anton Vorontsov wrote: > > Li, thanks for heads-up! > > One thing though: documentation says that Marvell PHY address is > 0x3, while old device tree and this patch: > > http://www.bitshrine.org/gpp/linux-fsl-2.6.23-MPC8313ERDB-add-default-dts.patch > > says "0x1"... I don't have any rev. C boards, so it would > be great if somebody could confirm that 0x1 is the actual address. Leo, on comments on this? - k ^ permalink raw reply [flat|nested] 13+ messages in thread
* RE: [PATCH] powerpc/83xx: Revive Marvell PHY option on MPC8313E-RDB rev. C boards 2009-02-12 5:24 ` Kumar Gala @ 2009-02-12 5:40 ` Li Yang-R58472 2009-02-12 23:51 ` Kumar Gala 0 siblings, 1 reply; 13+ messages in thread From: Li Yang-R58472 @ 2009-02-12 5:40 UTC (permalink / raw) To: Kumar Gala; +Cc: linuxppc-dev list > -----Original Message----- > From: Kumar Gala [mailto:galak@kernel.crashing.org]=20 > Sent: Thursday, February 12, 2009 1:25 PM > To: Li Yang-R58472 > Cc: linuxppc-dev list; Anton Vorontsov > Subject: Re: [PATCH] powerpc/83xx: Revive Marvell PHY option=20 > on MPC8313E-RDB rev. C boards >=20 >=20 > On Feb 10, 2009, at 9:10 AM, Anton Vorontsov wrote: >=20 > > > > Li, thanks for heads-up! > > > > One thing though: documentation says that Marvell PHY=20 > address is 0x3,=20 > > while old device tree and this patch: > > > >=20 > http://www.bitshrine.org/gpp/linux-fsl-2.6.23-MPC8313ERDB-add-default- > > dts.patch > > > > says "0x1"... I don't have any rev. C boards, so it would=20 > be great if=20 > > somebody could confirm that 0x1 is the actual address. The correct address is 0x3. The previous patch in revB BSP used a guess value before the revC documentation is available. The latest BSP has been updated to use the correct address. - Leo ^ permalink raw reply [flat|nested] 13+ messages in thread
* Re: [PATCH] powerpc/83xx: Revive Marvell PHY option on MPC8313E-RDB rev. C boards 2009-02-12 5:40 ` Li Yang-R58472 @ 2009-02-12 23:51 ` Kumar Gala 2009-02-13 1:18 ` Anton Vorontsov 0 siblings, 1 reply; 13+ messages in thread From: Kumar Gala @ 2009-02-12 23:51 UTC (permalink / raw) To: Anton Vorontsov; +Cc: linuxppc-dev list On Feb 11, 2009, at 11:40 PM, Li Yang-R58472 wrote: >> -----Original Message----- >> From: Kumar Gala [mailto:galak@kernel.crashing.org] >> Sent: Thursday, February 12, 2009 1:25 PM >> To: Li Yang-R58472 >> Cc: linuxppc-dev list; Anton Vorontsov >> Subject: Re: [PATCH] powerpc/83xx: Revive Marvell PHY option >> on MPC8313E-RDB rev. C boards >> >> >> On Feb 10, 2009, at 9:10 AM, Anton Vorontsov wrote: >> >>> >>> Li, thanks for heads-up! >>> >>> One thing though: documentation says that Marvell PHY >> address is 0x3, >>> while old device tree and this patch: >>> >>> >> http://www.bitshrine.org/gpp/linux-fsl-2.6.23-MPC8313ERDB-add- >> default- >>> dts.patch >>> >>> says "0x1"... I don't have any rev. C boards, so it would >> be great if >>> somebody could confirm that 0x1 is the actual address. > > The correct address is 0x3. The previous patch in revB BSP used a > guess > value before the revC documentation is available. The latest BSP has > been updated to use the correct address. Anton, will you spin a new patch with this change? - k ^ permalink raw reply [flat|nested] 13+ messages in thread
* Re: [PATCH] powerpc/83xx: Revive Marvell PHY option on MPC8313E-RDB rev. C boards 2009-02-12 23:51 ` Kumar Gala @ 2009-02-13 1:18 ` Anton Vorontsov 2009-02-13 2:24 ` [PATCH] powerpc/83xx: Revive Marvell PHY option onMPC8313E-RDB " Li Yang-R58472 0 siblings, 1 reply; 13+ messages in thread From: Anton Vorontsov @ 2009-02-13 1:18 UTC (permalink / raw) To: Kumar Gala; +Cc: linuxppc-dev list On Thu, Feb 12, 2009 at 05:51:57PM -0600, Kumar Gala wrote: > On Feb 11, 2009, at 11:40 PM, Li Yang-R58472 wrote: >>>> Li, thanks for heads-up! >>>> >>>> One thing though: documentation says that Marvell PHY >>> address is 0x3, >>>> while old device tree and this patch: >>>> >>>> >>> http://www.bitshrine.org/gpp/linux-fsl-2.6.23-MPC8313ERDB-add- >>> default- >>>> dts.patch >>>> >>>> says "0x1"... I don't have any rev. C boards, so it would >>> be great if >>>> somebody could confirm that 0x1 is the actual address. >> >> The correct address is 0x3. The previous patch in revB BSP used a >> guess >> value before the revC documentation is available. The latest BSP has >> been updated to use the correct address. > > Anton, will you spin a new patch with this change? Since the correct address is 0x3, that means that the old device tree never worked on rev. C boards, thus there is no regression. And furthermore, it appears that U-Boot doesn't support Marvell PHY option either. So, I don't think that adding the new device tree makes any sense now. I think the better option would be to implement Marvell PHY support in U-Boot, and at the same time teach U-Boot to fixup 8313rdb's device tree depending on the environment variable (something like setenv marvell_phy_option yes/no), i.e. like I did for MPC8315E-RDB's ULPI/TSEC1 options: http://lists.denx.de/pipermail/u-boot/2008-July/036553.html Makes sense? If not, I'll readily respin this patch with the PHY address change. Thanks, -- Anton Vorontsov email: cbouatmailru@gmail.com irc://irc.freenode.net/bd2 ^ permalink raw reply [flat|nested] 13+ messages in thread
* RE: [PATCH] powerpc/83xx: Revive Marvell PHY option onMPC8313E-RDB rev. C boards 2009-02-13 1:18 ` Anton Vorontsov @ 2009-02-13 2:24 ` Li Yang-R58472 0 siblings, 0 replies; 13+ messages in thread From: Li Yang-R58472 @ 2009-02-13 2:24 UTC (permalink / raw) To: avorontsov, Kumar Gala; +Cc: linuxppc-dev list > -----Original Message----- > From: Anton Vorontsov [mailto:avorontsov@ru.mvista.com]=20 > Sent: Friday, February 13, 2009 9:18 AM > To: Kumar Gala > Cc: linuxppc-dev list; Li Yang-R58472 > Subject: Re: [PATCH] powerpc/83xx: Revive Marvell PHY option=20 > onMPC8313E-RDB rev. C boards >=20 > On Thu, Feb 12, 2009 at 05:51:57PM -0600, Kumar Gala wrote: > > On Feb 11, 2009, at 11:40 PM, Li Yang-R58472 wrote: > >>>> Li, thanks for heads-up! > >>>> > >>>> One thing though: documentation says that Marvell PHY > >>> address is 0x3, > >>>> while old device tree and this patch: > >>>> > >>>> > >>> http://www.bitshrine.org/gpp/linux-fsl-2.6.23-MPC8313ERDB-add- > >>> default- > >>>> dts.patch > >>>> > >>>> says "0x1"... I don't have any rev. C boards, so it would > >>> be great if > >>>> somebody could confirm that 0x1 is the actual address. > >> > >> The correct address is 0x3. The previous patch in revB BSP used a=20 > >> guess value before the revC documentation is available. =20 > The latest=20 > >> BSP has been updated to use the correct address. > > > > Anton, will you spin a new patch with this change? >=20 > Since the correct address is 0x3, that means that the old=20 > device tree never worked on rev. C boards, thus there is no=20 > regression. > And furthermore, it appears that U-Boot doesn't support=20 > Marvell PHY option either. No regression but to be more updated. RevC boards are newly introduced. >=20 > So, I don't think that adding the new device tree makes any sense now. >=20 > I think the better option would be to implement Marvell PHY=20 > support in U-Boot, and at the same time teach U-Boot to fixup=20 > 8313rdb's device tree depending on the environment variable=20 > (something like setenv marvell_phy_option yes/no), i.e. like=20 > I did for MPC8315E-RDB's ULPI/TSEC1 options: >=20 > http://lists.denx.de/pipermail/u-boot/2008-July/036553.html This approach is surely more user friendly. - Leo ^ permalink raw reply [flat|nested] 13+ messages in thread
end of thread, other threads:[~2009-02-13 2:24 UTC | newest] Thread overview: 13+ messages (download: mbox.gz follow: Atom feed -- links below jump to the message on this page -- 2009-02-05 20:10 [PATCH 2/2] powerpc/83xx: Fix TSEC0 workability on MPC8313E-RDB boards Anton Vorontsov 2009-02-06 16:39 ` Kumar Gala 2009-02-09 7:47 ` Li Yang 2009-02-09 15:32 ` Kumar Gala 2009-02-10 15:10 ` [PATCH] powerpc/83xx: Revive Marvell PHY option on MPC8313E-RDB rev. C boards Anton Vorontsov 2009-02-10 15:30 ` Kumar Gala 2009-02-12 2:36 ` Li Yang-R58472 2009-02-12 5:25 ` Kumar Gala 2009-02-12 5:24 ` Kumar Gala 2009-02-12 5:40 ` Li Yang-R58472 2009-02-12 23:51 ` Kumar Gala 2009-02-13 1:18 ` Anton Vorontsov 2009-02-13 2:24 ` [PATCH] powerpc/83xx: Revive Marvell PHY option onMPC8313E-RDB " Li Yang-R58472
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