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From: David Jander <david.jander@protonic.nl>
To: Kumar Gala <galak@kernel.crashing.org>
Subject: Re: [RFC] [PATCH v2] MPC5121 TLB errata workaround
Date: Fri, 13 Mar 2009 15:24:36 +0100
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On Friday 13 March 2009 14:21:57 Kumar Gala wrote:
> >
> 
> What does cat /proc/cpuinfo show on this board?

# cat /proc/cpuinfo
processor       : 0
cpu             : e300c4
clock           : 400.000000MHz
revision        : 1.0 (pvr 8086 2010)
bogomips        : 99.84
timebase        : 50000000
platform        : MPC5121 Generic

> > +#ifdef CONFIG_PPC_MPC512x
> > +/* MPC512x: workaround for errata in die M36P and earlier:
> > + * Implement LRW for TLB way.
> > + */
> 
> This errata impacts a number of cores and so we should make this a CPU  
> feature fixup rather than #ifdef code.

It should impact only MPC5121e and probably MPC5123, but according to
Freescale no other processors that use this core...
Anyway, I'll try to investigate about how to write a "CPU feature fixup",
I've never done that before (If you could give me a hint?)

> > +       mfspr   r3,SPRN_DMISS
> > +       rlwinm  r3,r3,19,25,29 /* Get Address bits 19:15 */
> > +       lis     r2,lrw@ha       /* Search index in lrw[] */
> > +       addi    r2,r2,lrw@l
> > +       tophys(r2,r2)
> > +       lwzx    r1,r3,r2       /* Get item from lrw[] */
> > +       cmpwi   0,r1,0         /* Was it way 0 last time? */
> 
> Why not use a bit vector since we only need one bit of information.   
> Additionally we can use a single SPRG at that point instead to keep  
> track of the LRU information.

Sounds interesting. I am just learning my first steps in powerpc-assembly, so
please forgive if this is a little inefficient still. I'll try again next week.

Greetings,

-- 
David Jander
Protonic Holland.