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Date: Wed, 20 May 2009 19:57:06 +0200
From: Wolfram Sang <w.sang@pengutronix.de>
To: Grant Likely <grant.likely@secretlab.ca>
Subject: Re: mpc5200 fec error
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> Yes, that sounds familiar.  Most likely, the value of the MDIO bus
> control register got clobbered and not reset when the FEC was reset.

I recall that I wondered about the RFIFO-error case back then. The manual s=
tates

=3D=3D=3D

Receive FIFO Error - indicates error occurred within the RX FIFO. When
RFIFO_ERROR bit is set, ECNTRL.ETHER_EN is cleared, halting FEC frame
processing. When this occurs, software must ensure both the FIFO Controller=
 and
BestComm are soft-reset.

=3D=3D=3D

It does not say that the whole FEC needs to be reset. (BTW doing a full FEC
reset in IRQ context caused OOPSes back then, have to dig up details, as it
doesn't seem to happen here...)

Regards,

   Wolfram

--=20
Pengutronix e.K.                           | Wolfram Sang                |
Industrial Linux Solutions                 | http://www.pengutronix.de/  |

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