[Patch 0/6] PPC64: Hardware Breakpoint interfaces - ver IV

["K.Prasad" <prasad@linux.vnet.ibm.com>]

Hi All,
	Please find a new patchset that implements Hardware Breakpoint interfaces
for PPC64 architecture, the previous version of which was posted here:
http://ozlabs.org/pipermail/linuxppc-dev/2009-May/072387.html and the changes over
it are mentioned in the changelog below.

Changelog - ver IV
------------------
(Ver I: http://ozlabs.org/pipermail/linuxppc-dev/2009-May/071942.html)
(Ver II: http://ozlabs.org/pipermail/linuxppc-dev/2009-May/072106.html)
(Ver III: http://ozlabs.org/pipermail/linuxppc-dev/2009-May/072387.html

- While DABR register requires double-word (8 bytes) aligned addresses, i.e.
the breakpoint is active over a range of 8 bytes, PPC64 allows byte-level
addressability. This may lead to stray exceptions which have to be ignored in
hw_breakpoint_handler(), when DAR != (Breakpoint request address). However DABR
will be populated with the requested breakpoint address aligned to the previous
double-word address. The code is now modified to store user-requested address
in 'bp->info.address' but update the DABR with a double-word aligned address.

- Please note that the Data Breakpoint facility in Xmon is broken as of 2.6.29
and the same has not been integrated into this facility as described in Ver I.

Kindly review the patches and let me know if they're in a form that is ready for
upstream inclusion.

Thanks,
K.Prasad