From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from e28smtp01.in.ibm.com (e28smtp01.in.ibm.com [59.145.155.1]) (using TLSv1 with cipher DHE-RSA-AES256-SHA (256/256 bits)) (Client CN "e28smtp01.in.ibm.com", Issuer "Equifax" (verified OK)) by ozlabs.org (Postfix) with ESMTPS id 5ADFBDE0CC for ; Thu, 4 Jun 2009 02:35:34 +1000 (EST) Received: from d28relay04.in.ibm.com (d28relay04.in.ibm.com [9.184.220.61]) by e28smtp01.in.ibm.com (8.13.1/8.13.1) with ESMTP id n53GZSoc020157 for ; Wed, 3 Jun 2009 22:05:28 +0530 Received: from d28av04.in.ibm.com (d28av04.in.ibm.com [9.184.220.66]) by d28relay04.in.ibm.com (8.13.8/8.13.8/NCO v9.2) with ESMTP id n53GZSAM2130172 for ; Wed, 3 Jun 2009 22:05:28 +0530 Received: from d28av04.in.ibm.com (loopback [127.0.0.1]) by d28av04.in.ibm.com (8.13.1/8.13.3) with ESMTP id n53GZRdL005029 for ; Thu, 4 Jun 2009 02:35:28 +1000 Date: Wed, 3 Jun 2009 22:05:24 +0530 From: "K.Prasad" To: David Gibson , linuxppc-dev@ozlabs.org Subject: [Patch 3/6] Modify ptrace code to use Hardware Breakpoint interfaces Message-ID: <20090603163524.GD5197@in.ibm.com> References: <20090603162741.197115376@prasadkr_t60p.in.ibm.com> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Cc: Michael Neuling , Benjamin Herrenschmidt , paulus@samba.org, Alan Stern , "K.Prasad" , Roland McGrath List-Id: Linux on PowerPC Developers Mail List List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Modify the ptrace code to use the hardware breakpoint interfaces for user-space. Signed-off-by: K.Prasad --- arch/powerpc/kernel/ptrace.c | 47 +++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 47 insertions(+) Index: linux-2.6-tip.hbkpt/arch/powerpc/kernel/ptrace.c =================================================================== --- linux-2.6-tip.hbkpt.orig/arch/powerpc/kernel/ptrace.c +++ linux-2.6-tip.hbkpt/arch/powerpc/kernel/ptrace.c @@ -37,6 +37,7 @@ #include #include #include +#include /* * does not yet catch signals sent when the child dies. @@ -735,9 +736,26 @@ void user_disable_single_step(struct tas clear_tsk_thread_flag(task, TIF_SINGLESTEP); } +void ptrace_triggered(struct hw_breakpoint *bp, struct pt_regs *regs) +{ + /* + * Unregister the breakpoint request here since ptrace has defined a + * one-shot behaviour for breakpoint exceptions in PPC64. + * The SIGTRAP signal is generated automatically for us in do_dabr(). + * We don't have to do anything here + */ + unregister_user_hw_breakpoint(current, bp); + kfree(bp); +} + int ptrace_set_debugreg(struct task_struct *task, unsigned long addr, unsigned long data) { +#ifdef CONFIG_PPC64 + struct thread_struct *thread = &(task->thread); + struct hw_breakpoint *bp; + int ret; +#endif /* For ppc64 we support one DABR and no IABR's at the moment (ppc64). * For embedded processors we support one DAC and no IAC's at the * moment. @@ -767,6 +785,35 @@ int ptrace_set_debugreg(struct task_stru if (data && !(data & DABR_TRANSLATION)) return -EIO; +#ifdef CONFIG_PPC64 + bp = thread->hbp[0]; + if (data == 0) { + if (bp) { + unregister_user_hw_breakpoint(task, bp); + kfree(bp); + } + return 0; + } + + if (bp) { + bp->info.type = data & HW_BREAKPOINT_RW; + task->thread.dabr = bp->info.address = data; + return modify_user_hw_breakpoint(task, bp); + } + bp = kzalloc(sizeof(struct hw_breakpoint), GFP_KERNEL); + if (!bp) + return -ENOMEM; + + /* Store the type of breakpoint */ + bp->info.type = data & HW_BREAKPOINT_RW; + bp->triggered = ptrace_triggered; + task->thread.dabr = bp->info.address = data; + + ret = register_user_hw_breakpoint(task, bp); + if (ret) + return ret; +#endif /* CONFIG_PPC64 */ + /* Move contents to the DABR register */ task->thread.dabr = data;