Can't write value into memory ?(E500 V2)

Can't write value into memory ?(E500 V2)

[wilbur.chan]

In  an assemblely code ,   I invalided all the TLB entries except for
the entry  we are executed in.

After that , I setuped a 1:1 TLB entry mapping of 1GB .

At last , I wrote value 30 into the physical address 0x0400,0000 (also
the virtual address because of my 1:1 mapping).

However, it seemed failed to store the value '30' at address
0x400,0000. The following is my code:

//code start

// setup a 1:1 mapping of 1GB
...
//store '30' into address 0x0400,0000

li  r23, 30
lis r22, 0x400
ori r22,r22,0x0
stb  r23,0(r22)


//check if we successfully store value at 0x400,0000

lis r22, 0x400
ori r22,r22,0x0
lwz r23,0(r22)
cmpw r23, 30
beq  print_equal

1: b 1b

print_equal:
 ...
//code end

I found that, print_equal was not called ,the whole code seemed  to
enter an  infinite loop.

Can anyone plz tell me why this happended?


Thanks in advance.


regards,

wilbur

Re: Can't write value into memory ?(E500 V2)

[Scott Wood]

On Wed, Aug 26, 2009 at 10:39:24PM +0800, wilbur.chan wrote:
> In  an assemblely code ,   I invalided all the TLB entries except for
> the entry  we are executed in.
> 
> After that , I setuped a 1:1 TLB entry mapping of 1GB .

What is it you're trying to do?

> At last , I wrote value 30 into the physical address 0x0400,0000 (also
> the virtual address because of my 1:1 mapping).
> 
> However, it seemed failed to store the value '30' at address
> 0x400,0000. The following is my code:
> 
> //code start
> 
> // setup a 1:1 mapping of 1GB
> ...

"..." is not code. :-)

> //store '30' into address 0x0400,0000
> 
> li  r23, 30
> lis r22, 0x400
> ori r22,r22,0x0
> stb  r23,0(r22)
> 
> 
> //check if we successfully store value at 0x400,0000
> 
> lis r22, 0x400
> ori r22,r22,0x0
> lwz r23,0(r22)
> cmpw r23, 30

The values should not be equal, since you wrote a byte and read back a
word.

Furthermore, you are storing the constant 30, but are comparing r23 with
the register r30 (I never liked that aspect of ppc asm syntax -- too
error prone).  If you want to compare with the constant 30, use "cmpwi".

> beq  print_equal
> 
> 1: b 1b
> 
> print_equal:
>  ...
> //code end
> 
> I found that, print_equal was not called ,the whole code seemed  to
> enter an  infinite loop.

That's because you have an infinite loop in your code, right after "beq
print_equal".

-Scott

Re: Can't write value into memory ?(E500 V2)

[wilbur.chan]

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2009/8/27 Scott Wood <scottwood@freescale.com>

>
> > //check if we successfully store value at 0x400,0000
> >
> > lis r22, 0x400
> > ori r22,r22,0x0
> > lwz r23,0(r22)
> > cmpw r23, 30
>
> The values should not be equal, since you wrote a byte and read back a
> word.
>
> Furthermore, you are storing the constant 30, but are comparing r23 with
> the register r30 (I never liked that aspect of ppc asm syntax -- too
> error prone).  If you want to compare with the constant 30, use "cmpwi".
>
> > beq  print_equal
> >
> > 1: b 1b
> >
> > print_equal:
> >  ...
> > //code end
> >
> > I found that, print_equal was not called ,the whole code seemed  to
> > enter an  infinite loop.
>
> That's because you have an infinite loop in your code, right after "beq
> print_equal".
>
> -Scott
>



Thank you very much.

I am using a SMP E500 v2, and I want CPU0 to write some value to a physical
address, and

wait for CPU1 to read from it.

However, it seemed failed to communicate between CPUs by DRAM..  CPU1 can
not read

the correct value from the address where CPU1 wrote to.

BTW: the physical address is  at 16M .

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Re: Can't write value into memory ?(E500 V2)

[Scott Wood]

wilbur.chan wrote:
> I am using a SMP E500 v2, and I want CPU0 to write some value to a 
> physical address, and  wait for CPU1 to read from it.

Is this under Linux (it is a Linux mailing list...)?  If so, there are 
better ways of communicating that don't involve clobbering random memory 
and overlapping userspace TLB mappings.

> However, it seemed failed to communicate between CPUs by DRAM..  CPU1 
> can not read
>  
> the correct value from the address where CPU1 wrote to.

Do both cores have a mapping with the M bit (memory coherence required) set?

-Scott

Re: Can't write value into memory ?(E500 V2)

[wilbur.chan]

2009/8/27 Scott Wood <scottwood@freescale.com>:
>
> Is this under Linux (it is a Linux mailing list...)? =A0If so, there are
> better ways of communicating that don't involve clobbering random memory =
and
> overlapping userspace TLB mappings.

Yes, I'm doing this under linux in kernel mode.

I've used interrupt between cores, to make:

1) cpu0  carrys some data to a place (As a matter of fact ,the 'data'
is a kernel, the 'place' is at 0, and  I'm using kexec..)

2) cpu0 writes a 'flag' to a physical address(16M), to indicate that ,

it has finished the carrying in step 1. And jump to new kernel directly.


3) cpu1 enters the loop by IRQ , checking the 'flag' from time to
time. If the 'flag' is true, it

breaks the  loop and jumps to the instruction in new kernel.


> Do both cores have a mapping with the M bit (memory coherence required) s=
et?


What do you mean by  M bit set?

I setup a 1:1 mapping in both cpu0 and cpu1, and invalidate all the
other entries in TLB1 and

TLB0

Re: Can't write value into memory ?(E500 V2)

[Scott Wood]

wilbur.chan wrote:
> 2009/8/27 Scott Wood <scottwood@freescale.com>:
>> Is this under Linux (it is a Linux mailing list...)?  If so, there are
>> better ways of communicating that don't involve clobbering random memory and
>> overlapping userspace TLB mappings.
> 
> Yes, I'm doing this under linux in kernel mode.
> 
> I've used interrupt between cores, to make:
> 
> 1) cpu0  carrys some data to a place (As a matter of fact ,the 'data'
> is a kernel, the 'place' is at 0, and  I'm using kexec..)
> 
> 2) cpu0 writes a 'flag' to a physical address(16M), to indicate that ,
> 
> it has finished the carrying in step 1. And jump to new kernel directly.

OK, so it's not really "under Linux" but "between Linuxes". :-)

Don't forget to clean the cache out on the destination core -- icache is 
not coherent with dcache.

> 3) cpu1 enters the loop by IRQ , checking the 'flag' from time to
> time. If the 'flag' is true, it
> 
> breaks the  loop and jumps to the instruction in new kernel.
> 
> 
>> Do both cores have a mapping with the M bit (memory coherence required) set?
> 
> 
> What do you mean by  M bit set?

There is a bit in MAS2, labelled "M", that you must set when writing the 
TLB entry for the mapping to be coherent across cores.

-Scott