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Date: Fri, 2 Oct 2009 20:08:48 +0200
From: Guillaume Knispel <gknispel@proformatique.com>
To: Michael Barkowski <michaelbarkowski@ruggedcom.com>
Subject: Re: Is volatile always verboten for FSL QE structures?
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Cc: Guillaume Knispel <gknispel@proformatique.com>, linuxppc-dev@ozlabs.org,
	Timur Tabi <timur@freescale.com>
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Michael Barkowski wrote:

> Kumar Gala wrote:
> > 
> > On Oct 2, 2009, at 9:46 AM, Timur Tabi wrote:
> > 
> >> Michael Barkowski wrote:
> >>> Just wondering - is there a case where using volatile for UCC
> >>> parameter RAM for example will not work, or is the use of I/O
> >>> accessors everywhere an attempt to be portable to other architectures?
> >>
> >> 'volatile' just doesn't really do what you think it should do.  The
> >> PowerPC architecture is too complicated w.r.t. ordering of reads and
> >> writes.  In other words, you can't trust it.
> >>
> >> No one should be using 'volatile' to access I/O registers.
> > 
> > See Documentation/volatile-considered-harmful.txt
> > 
> 
> I'm happy to adopt your interpretation of it, and I appreciate the explanation.
> 
> from Documentation/volatile-considered-harmful.txt:
> >   - The above-mentioned accessor functions might use volatile on
> >     architectures where direct I/O memory access does work.  Essentially,
> >     each accessor call becomes a little critical section on its own and
> >     ensures that the access happens as expected by the programmer.
> 
> Part of it was that I wondered if this was one of those architectures.  I guess not.

I guess this could only work on architectures having a totally ordered
memory model.  Definitely not the case for Power.