Re: Is volatile always verboten for FSL QE structures?

[Simon Richter <Simon.Richter@hogyros.de>]

Hi,

> > >> 'volatile' just doesn't really do what you think it should do.  The
> > >> PowerPC architecture is too complicated w.r.t. ordering of reads and
> > >> writes.  In other words, you can't trust it.

It's not sufficient on PowerPC.

It might be necessary, depending on the compiler's mood for moving stuff
out of loops.

Consider:

| unsigned int *foo = (unsigned int *)0x12345678;
| void bar(void) { while(*foo != 0) asm("eieio"); }

gcc 4.3.4 with -O3 compiles this to

00000000 <bar>:
   0:   3d 20 00 00     lis     r9,0
                        2: R_PPC_ADDR16_HA      foo
   4:   81 69 00 00     lwz     r11,0(r9)
                        6: R_PPC_ADDR16_LO      foo
   8:   80 0b 00 00     lwz     r0,0(r11)
   c:   2f 80 00 00     cmpwi   cr7,r0,0
  10:   4d 9e 00 20     beqlr   cr7
  14:   7c 00 06 ac     eieio
  18:   7c 00 06 ac     eieio
  1c:   4b ff ff f8     b       14 <bar+0x14>

Making the target of foo volatile properly rechecks the condition on
each iteration.

OTOH my PPC box runs fine, so I'm probably missing something obvious.

   Simon