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Date: Fri, 30 Oct 2009 12:37:49 -0500
From: Scott Wood <scottwood@freescale.com>
To: Joakim Tjernlund <joakim.tjernlund@transmode.se>
Subject: Re: [PATCH 0/8]  Fix 8xx MMU/TLB
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Cc: Rex Feany <RFeany@mrv.com>,
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On Fri, Oct 30, 2009 at 12:16:07PM -0500, Scott Wood wrote:
> On Sat, Oct 17, 2009 at 02:01:38PM +0200, Joakim Tjernlund wrote:
> > +     mfspr r10, SPRN_SRR0
> >       DO_8xx_CPU6(0x3780, r3)
> >       mtspr SPRN_MD_EPN, r10
> >       mfspr r11, SPRN_M_TWB	/* Get level 1 table entry address */
> > -     lwz   r11, 0(r11)	/* Get the level 1 entry */
> > +     cmplwi      cr0, r11, 0x0800
> > +     blt-  3f		/* Branch if user space */
> > +     lis   r11, swapper_pg_dir@h
> > +     ori   r11, r11, swapper_pg_dir@l
> > +     rlwimi      r11, r11, 0, 2, 19
> 
> That rlwimi is a no-op -- I think you meant to use a different register
> here?
> 
> > +3:   lwz   r11, 0(r11)	/* Get the level 1 entry */
> >       DO_8xx_CPU6(0x3b80, r3)
> >       mtspr SPRN_MD_TWC, r11	/* Load pte table base address */
> >       mfspr r11, SPRN_MD_TWC	/* ....and get the pte address */
> >       lwz   r11, 0(r11)	/* Get the pte */
> >       /* concat physical page address(r11) and page offset(r10) */
> >       rlwimi      r11, r10, 0, 20, 31
> 
> But r10 here contains SRR0 from above, and this is a data TLB error.

Never mind that last one, forgot that you'd be wanting to load the
instruction. :-P

But the rlwimi is what's causing the machine checks.  I replaced it with:
rlwinm	r11, r11, 0, 0x3ffff000
rlwimi	r11, r10, 22, 0xffc

and things seem to work.  You could probably replace the rlwinm by
subtracting PAGE_OFFSET from swapper_pg_dir instead.

-Scott