From: Anton Blanchard <anton@samba.org>
To: benh@kernel.crashing.org
Cc: npiggin@suse.de, linuxppc-dev@ozlabs.org
Subject: [PATCH 6/6] powerpc: Use lwsync for acquire barrier if CPU supports it
Date: Wed, 10 Feb 2010 22:10:25 +1100 [thread overview]
Message-ID: <20100210111025.GF3399@kryten> (raw)
In-Reply-To: <20100210110719.GE3399@kryten>
Nick Piggin discovered that lwsync barriers around locks were faster than isync
on 970. That was a long time ago and I completely dropped the ball in testing
his patches across other ppc64 processors.
Turns out the idea helps on other chips. Using a microbenchmark that
uses a lot of threads to contend on a global pthread mutex (and therefore a
global futex), POWER6 improves 8% and POWER7 improves 2%. I checked POWER5
and while I couldn't measure an improvement, there was no regression.
This patch uses the lwsync patching code to replace the isyncs with lwsyncs
on CPUs that support the instruction. We were marking POWER3 and RS64 as lwsync
capable but in reality they treat it as a full sync (ie slow). Remove the
CPU_FTR_LWSYNC bit from these CPUs so they continue to use the faster isync
method.
Signed-off-by: Anton Blanchard <anton@samba.org>
---
Index: powerpc.git/arch/powerpc/include/asm/synch.h
===================================================================
--- powerpc.git.orig/arch/powerpc/include/asm/synch.h 2010-02-10 17:16:44.666823141 +1100
+++ powerpc.git/arch/powerpc/include/asm/synch.h 2010-02-10 17:16:45.123073249 +1100
@@ -37,7 +37,11 @@ static inline void isync(void)
#endif
#ifdef CONFIG_SMP
-#define PPC_ACQUIRE_BARRIER "\n\tisync\n"
+#define __PPC_ACQUIRE_BARRIER \
+ START_LWSYNC_SECTION(97); \
+ isync; \
+ MAKE_LWSYNC_SECTION_ENTRY(97, __lwsync_fixup);
+#define PPC_ACQUIRE_BARRIER "\n" stringify_in_c(__PPC_ACQUIRE_BARRIER)
#define PPC_RELEASE_BARRIER stringify_in_c(LWSYNC) "\n"
#else
#define PPC_ACQUIRE_BARRIER
Index: powerpc.git/arch/powerpc/include/asm/cputable.h
===================================================================
--- powerpc.git.orig/arch/powerpc/include/asm/cputable.h 2010-02-10 17:15:59.816823326 +1100
+++ powerpc.git/arch/powerpc/include/asm/cputable.h 2010-02-10 17:16:45.123073249 +1100
@@ -381,9 +381,9 @@ extern const char *powerpc_base_platform
#define CPU_FTRS_GENERIC_32 (CPU_FTR_COMMON | CPU_FTR_NODSISRALIGN)
/* 64-bit CPUs */
-#define CPU_FTRS_POWER3 (CPU_FTR_USE_TB | CPU_FTR_LWSYNC | \
+#define CPU_FTRS_POWER3 (CPU_FTR_USE_TB | \
CPU_FTR_IABR | CPU_FTR_PPC_LE)
-#define CPU_FTRS_RS64 (CPU_FTR_USE_TB | CPU_FTR_LWSYNC | \
+#define CPU_FTRS_RS64 (CPU_FTR_USE_TB | \
CPU_FTR_IABR | \
CPU_FTR_MMCRA | CPU_FTR_CTRL)
#define CPU_FTRS_POWER4 (CPU_FTR_USE_TB | CPU_FTR_LWSYNC | \
next prev parent reply other threads:[~2010-02-10 11:10 UTC|newest]
Thread overview: 19+ messages / expand[flat|nested] mbox.gz Atom feed top
2010-02-10 10:57 [PATCH 1/6] powerpc: Use lwarx hint in spinlocks Anton Blanchard
2010-02-10 11:02 ` [PATCH 2/6] powerpc: Use lwarx/ldarx hint in bit locks Anton Blanchard
2010-02-10 11:03 ` [PATCH 3/6] powerpc: Convert open coded native hashtable bit lock Anton Blanchard
2010-02-10 11:04 ` [PATCH 4/6] powerpc: Rename LWSYNC_ON_SMP to PPC_RELEASE_BARRIER, ISYNC_ON_SMP to PPC_ACQUIRE_BARRIER Anton Blanchard
2010-02-10 11:07 ` [PATCH 5/6] powerpc: Fix lwsync patching code on 64bit Anton Blanchard
2010-02-10 11:10 ` Anton Blanchard [this message]
2010-02-11 7:09 ` [PATCH 6/6] powerpc: Use lwsync for acquire barrier if CPU supports it Nick Piggin
2010-02-17 9:43 ` Anton Blanchard
2010-02-17 10:41 ` Nick Piggin
2010-02-17 12:12 ` Benjamin Herrenschmidt
2010-02-16 4:22 ` Olof Johansson
2010-02-16 4:19 ` Benjamin Herrenschmidt
2010-02-16 6:07 ` Olof Johansson
2010-03-19 1:08 ` [PATCH 4/6] powerpc: Rename LWSYNC_ON_SMP to PPC_RELEASE_BARRIER, ISYNC_ON_SMP to PPC_ACQUIRE_BARRIER Nick Piggin
2010-03-19 1:36 ` Benjamin Herrenschmidt
2010-02-11 6:56 ` [PATCH 1/6] powerpc: Use lwarx hint in spinlocks Nick Piggin
2010-02-17 9:37 ` Anton Blanchard
2010-02-17 10:22 ` Nick Piggin
2010-02-16 4:16 ` Olof Johansson
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