From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from TX2EHSOBE006.bigfish.com (tx2ehsobe003.messaging.microsoft.com [65.55.88.13]) (using TLSv1 with cipher AES128-SHA (128/128 bits)) (Client CN "mail.global.frontbridge.com", Issuer "Cybertrust SureServer Standard Validation CA" (verified OK)) by ozlabs.org (Postfix) with ESMTPS id 9C675B6F07 for ; Wed, 13 Oct 2010 08:22:12 +1100 (EST) Received: from mail93-tx2 (localhost.localdomain [127.0.0.1]) by mail93-tx2-R.bigfish.com (Postfix) with ESMTP id A663A19C06A7 for ; Tue, 12 Oct 2010 21:21:55 +0000 (UTC) Received: from TX2EHSMHS023.bigfish.com (unknown [10.9.14.246]) by mail93-tx2.bigfish.com (Postfix) with ESMTP id 66996FD005C for ; Tue, 12 Oct 2010 21:21:55 +0000 (UTC) Received: from az33smr02.freescale.net (az33smr02.freescale.net [10.64.34.200]) by az33egw02.freescale.net (8.14.3/8.14.3) with ESMTP id o9CLLsuN028527 for ; Tue, 12 Oct 2010 14:21:54 -0700 (MST) Received: from az33exm25.fsl.freescale.net (az33exm25.am.freescale.net [10.64.32.16]) by az33smr02.freescale.net (8.13.1/8.13.0) with ESMTP id o9CLLrqE019166 for ; Tue, 12 Oct 2010 16:21:53 -0500 (CDT) Date: Tue, 12 Oct 2010 16:21:52 -0500 From: Scott Wood To: Subject: Re: Questions on interrupt vector assignment on MPC8641D Message-ID: <20101012162152.5246744a@udp111988uds.am.freescale.net> In-Reply-To: <942ea2f3464025464521511c32355782.squirrel@localhost> References: <6e7b840fa55e4fba421e1b1cea2716ec.squirrel@localhost> <1682399277683944B902B3657D2FCE21654570D791@CAREXCLUSTER03.ATL.CW.LOCAL> <20100921170700.53a99e56@udp111988uds.am.freescale.net> <20101007152626.4e834d43@udp111988uds.am.freescale.net> <8636b70ea34330679bebdaad187ccd68.squirrel@localhost> <4CB2DEFB.90204@windriver.com> <20101011121745.2e471fc0@udp111988uds.am.freescale.net> <942ea2f3464025464521511c32355782.squirrel@localhost> MIME-Version: 1.0 Content-Type: text/plain; charset="US-ASCII" Cc: "tiejun.chen" , "linuxppc-dev@lists.ozlabs.org" List-Id: Linux on PowerPC Developers Mail List List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , On Tue, 12 Oct 2010 15:55:28 -0500 wrote: > I wonder about the next lines: > > > mpic_assign_isu(mpic1, 0, res.start + 0x10000); > > /* 48 Internal Interrupts */ > mpic_assign_isu(mpic1, 1, res.start + 0x10200); > mpic_assign_isu(mpic1, 2, res.start + 0x10400); > mpic_assign_isu(mpic1, 3, res.start + 0x10600); > > /* 16 External interrupts > * Moving them from [0 - 15] to [64 - 79] > */ > mpic_assign_isu(mpic1, 4, res.start + 0x10000); No mainline 86xx boards do that, even in 2.6.26. I suspect you need to either get rid of the isu stuff altogether, or add a mapping for the MSI interrupts. > Looking at the code, and where it appears to be faulting, it looks like > its in kernel/irq/chip.c: > > > int set_irq_type(unsigned int irq, unsigned int type) > { > struct irq_desc *desc; > unsigned long flags; > int ret = -ENXIO; > > if (irq >= NR_IRQS) { > printk(KERN_ERR "Trying to set irq type for IRQ%d\n", irq); > return -ENODEV; > } > > desc = irq_desc + irq; > ------------------------ > if (desc->chip->set_type) { > spin_lock_irqsave(&desc->lock, flags); > ret = desc->chip->set_type(irq, type); > ------------------------ > > > spin_unlock_irqrestore(&desc->lock, flags); > } > return ret; > } > > My conjecture is that desc->chip isn't set. Is mpic_assign_isu the > function that does that? That happens in set_irq_chip_and_handler(), called from mpic_host_map() -- just a few lines before calling set_irq_type(). The crash is happening somewhere in mpic_set_irq_type(): > NIP [c0016540] mpic_set_irq_type+0x188/0x1c4 -Scott