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Date: Mon, 13 Dec 2010 11:51:31 -0600
From: Scott Wood <scottwood@freescale.com>
To: Joakim Tjernlund <joakim.tjernlund@transmode.se>
Subject: Re: MPC831x (and others?) NAND erase performance improvements
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On Mon, 13 Dec 2010 18:41:32 +0100
Joakim Tjernlund <joakim.tjernlund@transmode.se> wrote:

> Scott Wood <scottwood@freescale.com> wrote on 2010/12/13 18:33:56:
> >
> > On Mon, 13 Dec 2010 11:32:00 +0100
> > Joakim Tjernlund <joakim.tjernlund@transmode.se> wrote:
> >
> > > What if one has several NAND chips to build a big FS? Is the NAND
> > > controller equipped to handle that?
> >
> > FCM can drive one NAND chip per eLBC chipselect, though possibly you
> > could go beyond that with a board-logic chipselect mechanism.
> 
> hmm, then I guess one would have to use one GPIO/IRQ per NAND chip?

Couldn't you just tie together all the open-drain busy lines before you
invert it?  You'll only be driving one NAND chip at a time anyway; the
others should not be asserting busy.

-Scott