From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Date: Tue, 29 Mar 2011 11:34:34 -0700 From: Sarah Sharp To: Benjamin Herrenschmidt Subject: Re: [PATCH v2 5/5] xhci: Remove recursive call to xhci_handle_event Message-ID: <20110329183434.GA5720@xanatos> References: <4D8C47D8.4020901@ozlabs.org> <4D8C8F2B.9090808@ru.mvista.com> <4D90142C.4050206@ozlabs.org> <20110328223424.GF8065@xanatos> <1301356734.2402.657.camel@pasglop> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii In-Reply-To: <1301356734.2402.657.camel@pasglop> Cc: linuxppc-dev@ozlabs.org, linux-usb@vger.kernel.org, Sergei Shtylyov , Matt Evans List-Id: Linux on PowerPC Developers Mail List List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , On Tue, Mar 29, 2011 at 10:58:54AM +1100, Benjamin Herrenschmidt wrote: > On Mon, 2011-03-28 at 15:34 -0700, Sarah Sharp wrote: > > > > What I'd like to do is take out the read of the status register out of > > the interrupt handler (which is killing performance), and make it only > > check the status register when xhci_handle_event() returns a negative > > error status. If the status register shows the host controller has a > > critical error, the driver should call usb_hcd_died(). > > Be careful with removing that read... > > Without MSIs, that read is what guarantees that all pending DMA writes > by the xHCI have been "flushed" before you start poking at memory. > > IE. If the chip writes an event and sends an LSI, without that read, you > might get the interrupt before the writes to memory have completed and > your driver will "miss" the event. > > With MSIs (provided they are not broken on your PCI host bridge of > course, this is typically the #1 cause of MSI breakage), you don't need > that as the MSI itself is a DMA store by the device which is ordered > after the stores done to update the event. So by the time you get the > MSI interrupt, you -should- have all the updates visible in memory. > > But that means that your PCI host bridge is doing the right thing, by > ensuring whatever queues to the coherency domain it has have been > properly flushed before it signals the interrupts caused by the MSI to > the processors. Hopefully most systems get that right nowadays. > > Point is: you need to keep that read if MSIs aren't enabled. Sorry for the sloppy language, yes, I understand I still need the status register read if only legacy IRQs are enabled. Sarah Sharp