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Date: Fri, 24 Jun 2011 10:16:28 -0500
From: Scott Wood <scottwood@freescale.com>
To: Tabi Timur-B04825 <B04825@freescale.com>
Subject: Re: [PATCH] powerpc/85xx: disable timebase synchronization under
	the hypervisor
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On Thu, 23 Jun 2011 21:38:58 -0500
Tabi Timur-B04825 <B04825@freescale.com> wrote:

> Segher Boessenkool wrote:
> >
> > v2.06 III-E 9.2.1:
> > "Writing the Time Base is hypervisor privileged."
> >
> > v2.06 III-E 2.1:
> > "If a hypervisor-privileged register is accessed in the guest supervisor
> > state (MSR[GS PR] = 0b10), an Embedded Hypervisor Privilege exception
> > occurs."
> >
> > (v2.06 III-E 5.4.1, the big SPR table, also shows the TB regs (for writing,
> > i.e. 284 and 285) to be hypervisor privileged.  Consistency, hurray :-) )
> 
> To me, all this means that a guest cannot write to the actual timebase 
> register.  I'm not interpreting this to mean that a hypervisor can't 
> virtualize the timebase and allow a guest to read/write a virtual timebase 
> register, so that it thinks it's writing to the real hardware timebase register.
> 

Right, I was referring to the virtualized implementation note added in
2.06B.  The virtualized implementation notes apply to what happens in the
guest as seen by the guest (considered as a separate implementation of the
Power ISA), not to what happens at a hardware level in guest mode.

-Scott