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Date: Wed, 29 Jun 2011 14:40:10 -0500
From: Scott Wood <scottwood@freescale.com>
To: Benjamin Herrenschmidt <benh@kernel.crashing.org>
Subject: Re: [PATCH v2] powerpc/book3e-64: use a separate TLB handler when
	linear map is bolted
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On Wed, 29 Jun 2011 17:50:28 +1000
Benjamin Herrenschmidt <benh@kernel.crashing.org> wrote:

> On Wed, 2011-06-22 at 16:25 -0500, Scott Wood wrote:
> > On MMUs such as FSL where we can guarantee the entire linear mapping is
> > bolted, we don't need to worry about linear TLB misses.  If on top of
> > that we do a full table walk, we get rid of all recursive TLB faults, and
> > can dispense with some state saving.  This gains a few percent on
> > TLB-miss-heavy workloads, and around 50% on a benchmark that had a high
> > rate of virtual page table faults under the normal handler.
> > 
> > While touching the EX_TLB layout, remove EX_TLB_MMUCR0, EX_TLB_SRR0, and
> > EX_TLB_SRR1 as they're not used.
> 
> I merged that into -next, but it was breaking 64K pages on WSP, I had to
> add an ifdef in there to skip the PUD level when walking the page tables
> (PUD_SHIFT isn't defined for asm when doing 64K pages).
> 
> Please check I didn't break anything.

Looks good, though I wonder if all the bolted stuff should be under the
ifdef, at least for now.

What is the "weird page table format" referred to by the normal miss
handler?

-Scott