>From 4cf7463af262230fcc0db95b2f47b0dcbf76daa9 Mon Sep 17 00:00:00 2001 From: Anatolij Gustschin Date: Wed, 18 Jan 2012 01:01:06 +0100 Subject: [PATCH] usb: ehci-fsl: set INCR8 mode for system bus interface Port commit 69b4acc1dc4aa98a8f1016684fc99aba10156f87 (USB: Set INCR8 mode for system bus interface.) from Freescale ltib 2.6.24 kernel for mpc512x: This is a work-around for the USB-bus-hang problem observed on MPC512x when there is heavy simultaneous PATA write activity. See also "12.4 The USB controller can issue transactions that lock up the AHB bus under certain conditions" in MPC5121e (M36P) Errata Signed-off-by: Anatolij Gustschin --- drivers/usb/host/ehci-fsl.c | 10 ++++++++++ drivers/usb/host/ehci-fsl.h | 2 ++ 2 files changed, 12 insertions(+), 0 deletions(-) diff --git a/drivers/usb/host/ehci-fsl.c b/drivers/usb/host/ehci-fsl.c index e90344a..a6a6722 100644 --- a/drivers/usb/host/ehci-fsl.c +++ b/drivers/usb/host/ehci-fsl.c @@ -346,6 +346,14 @@ static int ehci_fsl_setup(struct usb_hcd *hcd) ehci_reset(ehci); +#ifdef CONFIG_PPC_MPC512x + /* + * set SBUSCFG:AHBBRST so that control msgs don't + * fail when doing heavy PATA writes. + */ + ehci_writel(ehci, SBUSCFG_INCR8, hcd->regs + FSL_SOC_USB_SBUSCFG); +#endif + retval = ehci_fsl_reinit(ehci); return retval; } @@ -469,6 +477,8 @@ static int ehci_fsl_mpc512x_drv_resume(struct device *dev) ehci_writel(ehci, ISIPHYCTRL_PXE | ISIPHYCTRL_PHYE, hcd->regs + FSL_SOC_USB_ISIPHYCTRL); + ehci_writel(ehci, SBUSCFG_INCR8, hcd->regs + FSL_SOC_USB_SBUSCFG); + /* restore EHCI registers */ ehci_writel(ehci, pdata->pm_command, &ehci->regs->command); ehci_writel(ehci, pdata->pm_intr_enable, &ehci->regs->intr_enable); diff --git a/drivers/usb/host/ehci-fsl.h b/drivers/usb/host/ehci-fsl.h index 4918062..0855be8 100644 --- a/drivers/usb/host/ehci-fsl.h +++ b/drivers/usb/host/ehci-fsl.h @@ -19,6 +19,8 @@ #define _EHCI_FSL_H /* offsets for the non-ehci registers in the FSL SOC USB controller */ +#define FSL_SOC_USB_SBUSCFG 0x90 +#define SBUSCFG_INCR8 0x02 /* INCR8, specified */ #define FSL_SOC_USB_ULPIVP 0x170 #define FSL_SOC_USB_PORTSC1 0x184 #define PORT_PTS_MSK (3<<30) -- 1.7.1