From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mail.8bytes.org (8bytes.org [85.214.48.195]) by ozlabs.org (Postfix) with ESMTP id BE5412C0084 for ; Wed, 27 Feb 2013 22:38:26 +1100 (EST) Received: from localhost (localhost [127.0.0.1]) by mail.8bytes.org (Postfix) with SMTP id 94C4612B0EE for ; Wed, 27 Feb 2013 12:38:23 +0100 (CET) Date: Wed, 27 Feb 2013 12:38:22 +0100 From: Joerg Roedel To: Varun Sethi Subject: Re: [PATCH 5/6 v8] iommu/fsl: Add addtional attributes specific to the PAMU driver. Message-ID: <20130227113822.GJ26252@8bytes.org> References: <1361191939-21260-1-git-send-email-Varun.Sethi@freescale.com> <1361191939-21260-6-git-send-email-Varun.Sethi@freescale.com> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii In-Reply-To: <1361191939-21260-6-git-send-email-Varun.Sethi@freescale.com> Cc: scottwood@freescale.com, iommu@lists.linux-foundation.org, linuxppc-dev@lists.ozlabs.org, linux-kernel@vger.kernel.org, stuart.yoder@freescale.com List-Id: Linux on PowerPC Developers Mail List List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , On Mon, Feb 18, 2013 at 06:22:18PM +0530, Varun Sethi wrote: > Added the following domain attributes for the FSL PAMU driver: > 1. Added new iommu stash attribute, which allows setting of the > LIODN specific stash id parameter through IOMMU API. > 2. Added an attribute for enabling/disabling DMA to a particular > memory window. > 3. Added domain attribute to check for PAMUV1 specific constraints. > > > Signed-off-by: Varun Sethi > --- > include/linux/iommu.h | 33 +++++++++++++++++++++++++++++++++ > 1 files changed, 33 insertions(+), 0 deletions(-) > > diff --git a/include/linux/iommu.h b/include/linux/iommu.h > index 529987c..c44e38b 100644 > --- a/include/linux/iommu.h > +++ b/include/linux/iommu.h > @@ -40,6 +40,23 @@ struct notifier_block; > typedef int (*iommu_fault_handler_t)(struct iommu_domain *, > struct device *, unsigned long, int, void *); > > +/* cache stash targets */ > +#define IOMMU_ATTR_CACHE_L1 1 > +#define IOMMU_ATTR_CACHE_L2 2 > +#define IOMMU_ATTR_CACHE_L3 3 > + > +/* This attribute corresponds to IOMMUs capable of generating > + * a stash transaction. A stash transaction is typically a > + * hardware initiated prefetch of data from memory to cache. > + * This attribute allows configuring stashig specific parameters > + * in the IOMMU hardware. > + */ > + > +struct iommu_stash_attribute { > + u32 cpu; /* cpu number */ > + u32 cache; /* cache to stash to: L1,L2,L3 */ > +}; Please make the cache-attribute an enum instead of using defines. Joerg