* Re: [PATCH] arch/powerpc: advertise ISA2.07, HTM, DSCR, EBB and ISEL bits in HWCAP2
2013-05-03 23:19 [PATCH] arch/powerpc: advertise ISA2.07, HTM, DSCR, EBB and ISEL bits in HWCAP2 Nishanth Aravamudan
@ 2013-05-03 23:23 ` Benjamin Herrenschmidt
2013-05-03 23:40 ` Nishanth Aravamudan
2013-05-03 23:26 ` Michael R Meissner
2013-05-04 0:04 ` Michael Neuling
2 siblings, 1 reply; 22+ messages in thread
From: Benjamin Herrenschmidt @ 2013-05-03 23:23 UTC (permalink / raw)
To: Nishanth Aravamudan
Cc: Michael Neuling, Michael R Meissner, sjmunroe, bergner,
Ryan Arnold, linuxppc-dev
On Fri, 2013-05-03 at 16:19 -0700, Nishanth Aravamudan wrote:
> +/* in AT_HWCAP2 */
> +#define PPC_FEATURE2_ARCH_2_07 0x80000000
> +#define PPC_FEATURE2_HTM 0x40000000
> +#define PPC_FEATURE2_DSCR 0x20000000
> +#define PPC_FEATURE2_EBB 0x10000000
> +#define PPC_FEATURE2_ISEL 0x08000000
Should we "adjust" (ie filter out) some of these based
on CONFIG_ options (such as transactional memory enabled,
EBB supported by the hypervisor, etc...) ?
Cheers,
Ben.
^ permalink raw reply [flat|nested] 22+ messages in thread
* Re: [PATCH] arch/powerpc: advertise ISA2.07, HTM, DSCR, EBB and ISEL bits in HWCAP2
2013-05-03 23:23 ` Benjamin Herrenschmidt
@ 2013-05-03 23:40 ` Nishanth Aravamudan
2013-05-06 14:38 ` Ryan Arnold
0 siblings, 1 reply; 22+ messages in thread
From: Nishanth Aravamudan @ 2013-05-03 23:40 UTC (permalink / raw)
To: Benjamin Herrenschmidt
Cc: Michael Neuling, Michael R Meissner, sjmunroe, bergner,
Ryan Arnold, linuxppc-dev
On 04.05.2013 [09:23:51 +1000], Benjamin Herrenschmidt wrote:
> On Fri, 2013-05-03 at 16:19 -0700, Nishanth Aravamudan wrote:
> > +/* in AT_HWCAP2 */
> > +#define PPC_FEATURE2_ARCH_2_07 0x80000000
> > +#define PPC_FEATURE2_HTM 0x40000000
> > +#define PPC_FEATURE2_DSCR 0x20000000
> > +#define PPC_FEATURE2_EBB 0x10000000
> > +#define PPC_FEATURE2_ISEL 0x08000000
>
> Should we "adjust" (ie filter out) some of these based
> on CONFIG_ options (such as transactional memory enabled,
> EBB supported by the hypervisor, etc...) ?
Err, yeah, that seems reasonable :) However, it seems like glibc uses
these values rather directly so it knows what bits to check for each
feature. Therefore, it seems like it would be better to do the
ifdeffery/checking in the user in cputable.c, but that seems like it
could get quite complicated.
Would it be ok (I guess I'm asking Ryan & co. here) to have an #ifdef in
the definition that may or may not mean the bit is set in the aux
vector, but the bit, if set, would always be the same bit?
-Nish
^ permalink raw reply [flat|nested] 22+ messages in thread
* Re: [PATCH] arch/powerpc: advertise ISA2.07, HTM, DSCR, EBB and ISEL bits in HWCAP2
2013-05-03 23:40 ` Nishanth Aravamudan
@ 2013-05-06 14:38 ` Ryan Arnold
2013-05-06 21:37 ` Benjamin Herrenschmidt
0 siblings, 1 reply; 22+ messages in thread
From: Ryan Arnold @ 2013-05-06 14:38 UTC (permalink / raw)
To: Nishanth Aravamudan
Cc: Michael R Meissner, Steve Munroe, Michael Neuling, Peter Bergner,
linuxppc-dev
[-- Attachment #1: Type: text/plain, Size: 2443 bytes --]
Nishanth Aravamudan <nacc@linux.vnet.ibm.com> wrote on 05/03/2013 06:40:19
PM:
> Nishanth Aravamudan <nacc@linux.vnet.ibm.com>
> 05/03/2013 06:40 PM
>
> To
>
> Benjamin Herrenschmidt <benh@kernel.crashing.org>
>
> cc
>
> Michael Neuling <michael.neuling@au1.ibm.com>, Michael R Meissner/
> Cambridge/IBM@IBMUS, Steve Munroe/Rochester/IBM@IBMUS, Peter
> Bergner/Rochester/IBM@IBMUS, Ryan Arnold/Rochester/IBM@IBMUS,
> linuxppc-dev@lists.ozlabs.org
>
> Subject
>
> Re: [PATCH] arch/powerpc: advertise ISA2.07, HTM, DSCR, EBB and ISEL
> bits in HWCAP2
>
> On 04.05.2013 [09:23:51 +1000], Benjamin Herrenschmidt wrote:
> > On Fri, 2013-05-03 at 16:19 -0700, Nishanth Aravamudan wrote:
> > > +/* in AT_HWCAP2 */
> > > +#define PPC_FEATURE2_ARCH_2_07 0x80000000
> > > +#define PPC_FEATURE2_HTM 0x40000000
> > > +#define PPC_FEATURE2_DSCR 0x20000000
> > > +#define PPC_FEATURE2_EBB 0x10000000
> > > +#define PPC_FEATURE2_ISEL 0x08000000
> >
> > Should we "adjust" (ie filter out) some of these based
> > on CONFIG_ options (such as transactional memory enabled,
> > EBB supported by the hypervisor, etc...) ?
>
> Err, yeah, that seems reasonable :) However, it seems like glibc uses
> these values rather directly so it knows what bits to check for each
> feature. Therefore, it seems like it would be better to do the
> ifdeffery/checking in the user in cputable.c, but that seems like it
> could get quite complicated.
>
> Would it be ok (I guess I'm asking Ryan & co. here) to have an #ifdef in
> the definition that may or may not mean the bit is set in the aux
> vector, but the bit, if set, would always be the same bit?
My understanding was that these bits being 'on' is an indication of what
features the hardware supports (or what the kernel emulates) and a not an
indication of whether that facility is currently enabled or not. If the
hardware supports a particular feature but it is not enabled I'd expect
that user-space usage of that feature would cause the kernel to trap on a
facility availability exception (which is how Altivec/VMX is implemented,
being defaulted to turned off).
Otherwise there's no way I could know whether an ISA [optional] feature is
actually available on a particular machine.
And yes, the bits can't change. My usage of hwcap.h has to coincide with
the kernel's asm/cputable.h
Ryan
[-- Attachment #2: Type: text/html, Size: 3457 bytes --]
^ permalink raw reply [flat|nested] 22+ messages in thread
* Re: [PATCH] arch/powerpc: advertise ISA2.07, HTM, DSCR, EBB and ISEL bits in HWCAP2
2013-05-06 14:38 ` Ryan Arnold
@ 2013-05-06 21:37 ` Benjamin Herrenschmidt
2013-05-07 15:11 ` Ryan Arnold
2013-05-07 20:33 ` Nishanth Aravamudan
0 siblings, 2 replies; 22+ messages in thread
From: Benjamin Herrenschmidt @ 2013-05-06 21:37 UTC (permalink / raw)
To: Ryan Arnold
Cc: linuxppc-dev, Nishanth Aravamudan, Steve Munroe, Peter Bergner,
Michael Neuling, Michael R Meissner
On Mon, 2013-05-06 at 09:38 -0500, Ryan Arnold wrote:
> My understanding was that these bits being 'on' is an indication of
> what features the hardware supports (or what the kernel emulates) and
> a not an indication of whether that facility is currently enabled or
> not. If the hardware supports a particular feature but it is not
> enabled I'd expect that user-space usage of that feature would cause
> the kernel to trap on a facility availability exception (which is how
> Altivec/VMX is implemented, being defaulted to turned off).
Right but the discussion is about whether we should expose the bits
when the kernel doesn't have the ability to handle the feature :-)
IE. We need to remove the HTM feature if the kernel is compiled without
transactional memory support.
Similarily, Nish, you may need to check that we remove those bits if
pHyp has the partition in a mode that doesn't support them (P7
compatibility for example) for migration purposes.
Cheers,
Ben.
> Otherwise there's no way I could know whether an ISA [optional]
> feature is actually available on a particular machine.
>
> And yes, the bits can't change. My usage of hwcap.h has to coincide
> with the kernel's asm/cputable.h
^ permalink raw reply [flat|nested] 22+ messages in thread
* Re: [PATCH] arch/powerpc: advertise ISA2.07, HTM, DSCR, EBB and ISEL bits in HWCAP2
2013-05-06 21:37 ` Benjamin Herrenschmidt
@ 2013-05-07 15:11 ` Ryan Arnold
2013-05-07 20:33 ` Nishanth Aravamudan
1 sibling, 0 replies; 22+ messages in thread
From: Ryan Arnold @ 2013-05-07 15:11 UTC (permalink / raw)
To: Benjamin Herrenschmidt
Cc: linuxppc-dev, Michael R Meissner, Steve Munroe, Peter Bergner,
Michael Neuling, Nishanth Aravamudan
[-- Attachment #1: Type: text/plain, Size: 1427 bytes --]
Benjamin Herrenschmidt <benh@kernel.crashing.org> wrote on 05/06/2013
04:37:08 PM:
> Benjamin Herrenschmidt <benh@kernel.crashing.org>
> 05/06/2013 04:37 PM
>
> To
>
> Ryan Arnold/Rochester/IBM@IBMUS
>
> cc
>
> Nishanth Aravamudan <nacc@linux.vnet.ibm.com>, linuxppc-
> dev@lists.ozlabs.org, Michael R Meissner/Cambridge/IBM@IBMUS,
> Michael Neuling <michael.neuling@au1.ibm.com>, Peter Bergner/
> Rochester/IBM@IBMUS, Steve Munroe/Rochester/IBM@IBMUS
>
> Subject
>
> Re: [PATCH] arch/powerpc: advertise ISA2.07, HTM, DSCR, EBB and ISEL
> bits in HWCAP2
>
> On Mon, 2013-05-06 at 09:38 -0500, Ryan Arnold wrote:
> > My understanding was that these bits being 'on' is an indication of
> > what features the hardware supports (or what the kernel emulates) and
> > a not an indication of whether that facility is currently enabled or
> > not. If the hardware supports a particular feature but it is not
> > enabled I'd expect that user-space usage of that feature would cause
> > the kernel to trap on a facility availability exception (which is how
> > Altivec/VMX is implemented, being defaulted to turned off).
>
> Right but the discussion is about whether we should expose the bits
> when the kernel doesn't have the ability to handle the feature :-)
>
> IE. We need to remove the HTM feature if the kernel is compiled without
> transactional memory support.
Thanks for explaining. This is exactly how it should work.
Ryan
[-- Attachment #2: Type: text/html, Size: 2115 bytes --]
^ permalink raw reply [flat|nested] 22+ messages in thread
* Re: [PATCH] arch/powerpc: advertise ISA2.07, HTM, DSCR, EBB and ISEL bits in HWCAP2
2013-05-06 21:37 ` Benjamin Herrenschmidt
2013-05-07 15:11 ` Ryan Arnold
@ 2013-05-07 20:33 ` Nishanth Aravamudan
2013-05-07 20:49 ` Benjamin Herrenschmidt
1 sibling, 1 reply; 22+ messages in thread
From: Nishanth Aravamudan @ 2013-05-07 20:33 UTC (permalink / raw)
To: Benjamin Herrenschmidt
Cc: linuxppc-dev, Michael R Meissner, Steve Munroe, Peter Bergner,
Ryan Arnold, Michael Neuling
On 07.05.2013 [07:37:08 +1000], Benjamin Herrenschmidt wrote:
> On Mon, 2013-05-06 at 09:38 -0500, Ryan Arnold wrote:
> > My understanding was that these bits being 'on' is an indication of
> > what features the hardware supports (or what the kernel emulates) and
> > a not an indication of whether that facility is currently enabled or
> > not. If the hardware supports a particular feature but it is not
> > enabled I'd expect that user-space usage of that feature would cause
> > the kernel to trap on a facility availability exception (which is how
> > Altivec/VMX is implemented, being defaulted to turned off).
>
> Right but the discussion is about whether we should expose the bits
> when the kernel doesn't have the ability to handle the feature :-)
>
> IE. We need to remove the HTM feature if the kernel is compiled without
> transactional memory support.
>
> Similarily, Nish, you may need to check that we remove those bits if
> pHyp has the partition in a mode that doesn't support them (P7
> compatibility for example) for migration purposes.
Yep, I'll need to talk with Mikey about this part. Will be a follow-on
patch if needed. Minimally, the bit defines will stay the same, which is
the important part to get going right now.
Thanks,
Nish
^ permalink raw reply [flat|nested] 22+ messages in thread
* Re: [PATCH] arch/powerpc: advertise ISA2.07, HTM, DSCR, EBB and ISEL bits in HWCAP2
2013-05-07 20:33 ` Nishanth Aravamudan
@ 2013-05-07 20:49 ` Benjamin Herrenschmidt
2013-05-07 21:11 ` Nishanth Aravamudan
0 siblings, 1 reply; 22+ messages in thread
From: Benjamin Herrenschmidt @ 2013-05-07 20:49 UTC (permalink / raw)
To: Nishanth Aravamudan
Cc: linuxppc-dev, Michael R Meissner, Steve Munroe, Peter Bergner,
Ryan Arnold, Michael Neuling
On Tue, 2013-05-07 at 13:33 -0700, Nishanth Aravamudan wrote:
> > Similarily, Nish, you may need to check that we remove those bits if
> > pHyp has the partition in a mode that doesn't support them (P7
> > compatibility for example) for migration purposes.
>
> Yep, I'll need to talk with Mikey about this part. Will be a follow-on
> patch if needed. Minimally, the bit defines will stay the same, which is
> the important part to get going right now.
Actually in such a mode we'd get a back-version architected PVR so we
should be fine now that I think twice, but of course that need to be
tested.
Cheers,
Ben.
^ permalink raw reply [flat|nested] 22+ messages in thread
* Re: [PATCH] arch/powerpc: advertise ISA2.07, HTM, DSCR, EBB and ISEL bits in HWCAP2
2013-05-07 20:49 ` Benjamin Herrenschmidt
@ 2013-05-07 21:11 ` Nishanth Aravamudan
0 siblings, 0 replies; 22+ messages in thread
From: Nishanth Aravamudan @ 2013-05-07 21:11 UTC (permalink / raw)
To: Benjamin Herrenschmidt
Cc: linuxppc-dev, Michael R Meissner, Steve Munroe, Peter Bergner,
Ryan Arnold, Michael Neuling
On 08.05.2013 [06:49:38 +1000], Benjamin Herrenschmidt wrote:
> On Tue, 2013-05-07 at 13:33 -0700, Nishanth Aravamudan wrote:
> > > Similarily, Nish, you may need to check that we remove those bits if
> > > pHyp has the partition in a mode that doesn't support them (P7
> > > compatibility for example) for migration purposes.
> >
> > Yep, I'll need to talk with Mikey about this part. Will be a follow-on
> > patch if needed. Minimally, the bit defines will stay the same, which is
> > the important part to get going right now.
>
> Actually in such a mode we'd get a back-version architected PVR so we
> should be fine now that I think twice, but of course that need to be
> tested.
True, I'll make sure it does get tested.
-Nish
^ permalink raw reply [flat|nested] 22+ messages in thread
* Re: [PATCH] arch/powerpc: advertise ISA2.07, HTM, DSCR, EBB and ISEL bits in HWCAP2
2013-05-03 23:19 [PATCH] arch/powerpc: advertise ISA2.07, HTM, DSCR, EBB and ISEL bits in HWCAP2 Nishanth Aravamudan
2013-05-03 23:23 ` Benjamin Herrenschmidt
@ 2013-05-03 23:26 ` Michael R Meissner
2013-05-04 21:42 ` Segher Boessenkool
2013-05-04 0:04 ` Michael Neuling
2 siblings, 1 reply; 22+ messages in thread
From: Michael R Meissner @ 2013-05-03 23:26 UTC (permalink / raw)
To: Nishanth Aravamudan
Cc: linuxppc-dev, Steve Munroe, Peter Bergner, Ryan Arnold,
Michael Neuling
[-- Attachment #1: Type: text/plain, Size: 4193 bytes --]
According to the GCC sources, ISEL is enabled by default for the 8540,
8548, e500mc, e500mc64, e6500 processors.
From:
Nishanth Aravamudan <nacc@linux.vnet.ibm.com>
To:
benh@kernel.crashing.org,
Cc:
Steve Munroe/Rochester/IBM@IBMUS, Peter Bergner/Rochester/IBM@IBMUS,
Michael R Meissner/Cambridge/IBM@IBMUS, Michael Neuling
<michael.neuling@au1.ibm.com>, linuxppc-dev@lists.ozlabs.org, Ryan
Arnold/Rochester/IBM@IBMUS
Date:
05/03/2013 07:19 PM
Subject:
[PATCH] arch/powerpc: advertise ISA2.07, HTM, DSCR, EBB and ISEL bits in
HWCAP2
Now that we have AT_HWCAP2 support, start exposing some of the new
POWER8 features via it.
Signed-off-by: Nishanth Aravamudan <nacc@us.ibm.com>
---
Note: there are, I think, some Freescale processors that also should be
updated to indicate they support ISEL, but I don't know which ones.
Since this is a new feature bit (and vector), it seems like we can fix
that up in a follow-on patch. Also, this is my first patch trying to
manipulate these bits, so please let me know if I'm doing something
wrong (for instance, I don't see any particular order to the bits in
PPC_FEATURE_*)
diff --git a/arch/powerpc/include/uapi/asm/cputable.h
b/arch/powerpc/include/uapi/asm/cputable.h
index ed9dd81..78db4e2 100644
--- a/arch/powerpc/include/uapi/asm/cputable.h
+++ b/arch/powerpc/include/uapi/asm/cputable.h
@@ -1,6 +1,7 @@
#ifndef _UAPI__ASM_POWERPC_CPUTABLE_H
#define _UAPI__ASM_POWERPC_CPUTABLE_H
+/* in AT_HWCAP */
#define PPC_FEATURE_32 0x80000000
#define PPC_FEATURE_64 0x40000000
#define PPC_FEATURE_601_INSTR 0x20000000
@@ -33,4 +34,11 @@
#define PPC_FEATURE_TRUE_LE 0x00000002
#define PPC_FEATURE_PPC_LE 0x00000001
+/* in AT_HWCAP2 */
+#define PPC_FEATURE2_ARCH_2_07 0x80000000
+#define PPC_FEATURE2_HTM 0x40000000
+#define PPC_FEATURE2_DSCR 0x20000000
+#define PPC_FEATURE2_EBB 0x10000000
+#define PPC_FEATURE2_ISEL 0x08000000
+
#endif /* _UAPI__ASM_POWERPC_CPUTABLE_H */
diff --git a/arch/powerpc/kernel/cputable.c
b/arch/powerpc/kernel/cputable.c
index ae9f433..871c741 100644
--- a/arch/powerpc/kernel/cputable.c
+++ b/arch/powerpc/kernel/cputable.c
@@ -102,6 +102,9 @@ extern void __restore_cpu_e6500(void);
PPC_FEATURE_SMT | PPC_FEATURE_ICACHE_SNOOP | \
PPC_FEATURE_TRUE_LE | \
PPC_FEATURE_PSERIES_PERFMON_COMPAT)
+#define COMMON_USER2_POWER8 (PPC_FEATURE2_ARCH_2_07 |
PPC_FEATURE2_HTM | \
+ PPC_FEATURE2_DSCR | PPC_FEATURE2_EBB | \
+ PPC_FEATURE2_ISEL)
#define COMMON_USER_PA6T (COMMON_USER_PPC64 |
PPC_FEATURE_PA6T |\
PPC_FEATURE_TRUE_LE | \
PPC_FEATURE_HAS_ALTIVEC_COMP)
@@ -443,6 +446,7 @@ static struct cpu_spec __initdata cpu_specs[] = {
.cpu_name =
"POWER8 (architected)",
.cpu_features =
CPU_FTRS_POWER8,
.cpu_user_features =
COMMON_USER_POWER8,
+ .cpu_user_features2 =
COMMON_USER2_POWER8,
.mmu_features =
MMU_FTRS_POWER8,
.icache_bsize =
128,
.dcache_bsize =
128,
@@ -492,6 +496,7 @@ static struct cpu_spec __initdata cpu_specs[] = {
.cpu_name =
"POWER8 (raw)",
.cpu_features =
CPU_FTRS_POWER8,
.cpu_user_features =
COMMON_USER_POWER8,
+ .cpu_user_features2 =
COMMON_USER2_POWER8,
.mmu_features =
MMU_FTRS_POWER8,
.icache_bsize =
128,
.dcache_bsize =
128,
[-- Attachment #2: Type: text/html, Size: 10342 bytes --]
^ permalink raw reply related [flat|nested] 22+ messages in thread* Re: [PATCH] arch/powerpc: advertise ISA2.07, HTM, DSCR, EBB and ISEL bits in HWCAP2
2013-05-03 23:26 ` Michael R Meissner
@ 2013-05-04 21:42 ` Segher Boessenkool
0 siblings, 0 replies; 22+ messages in thread
From: Segher Boessenkool @ 2013-05-04 21:42 UTC (permalink / raw)
To: Michael R Meissner
Cc: Michael Neuling, Nishanth Aravamudan, Steve Munroe, Peter Bergner,
Ryan Arnold, linuxppc-dev
> According to the GCC sources, ISEL is enabled by default for the
> 8540, 8548, e500mc, e500mc64, e6500 processors.
And e5500. POWER7 is said to support it as well.
Segher
^ permalink raw reply [flat|nested] 22+ messages in thread
* Re: [PATCH] arch/powerpc: advertise ISA2.07, HTM, DSCR, EBB and ISEL bits in HWCAP2
2013-05-03 23:19 [PATCH] arch/powerpc: advertise ISA2.07, HTM, DSCR, EBB and ISEL bits in HWCAP2 Nishanth Aravamudan
2013-05-03 23:23 ` Benjamin Herrenschmidt
2013-05-03 23:26 ` Michael R Meissner
@ 2013-05-04 0:04 ` Michael Neuling
2013-05-04 0:47 ` [PATCH v2 1/4] powerpc/cputable: reserve bits in HWCAP2 for new features Nishanth Aravamudan
2 siblings, 1 reply; 22+ messages in thread
From: Michael Neuling @ 2013-05-04 0:04 UTC (permalink / raw)
To: Nishanth Aravamudan
Cc: Michael R Meissner, Steve Munroe, Peter Bergner, Ryan Arnold,
linuxppc-dev
Nishanth Aravamudan <nacc@linux.vnet.ibm.com> wrote:
> Now that we have AT_HWCAP2 support, start exposing some of the new
> POWER8 features via it.
>
> Signed-off-by: Nishanth Aravamudan <nacc@us.ibm.com>
A few points:
We need a TAR bit as well, although this could be covered in 207?
For TM we need to turn it off if CONFIG_PPC_TRANSACTIONAL_MEM is not
set. Look at PPC_FEATURE_HAS_ALTIVEC_COMP for how we do that and follow
the bouncing ball.
Please add ISEL on other processors.
Please add DSCR on other processors.
EBB can be reserved, but there is no enablement at this point so don't
turn it on yet. We'll turn it on when we send the perf API.
Mikey
> ---
> Note: there are, I think, some Freescale processors that also should be
> updated to indicate they support ISEL, but I don't know which ones.
> Since this is a new feature bit (and vector), it seems like we can fix
> that up in a follow-on patch. Also, this is my first patch trying to
> manipulate these bits, so please let me know if I'm doing something
> wrong (for instance, I don't see any particular order to the bits in
> PPC_FEATURE_*)
>
> diff --git a/arch/powerpc/include/uapi/asm/cputable.h b/arch/powerpc/include/uapi/asm/cputable.h
> index ed9dd81..78db4e2 100644
> --- a/arch/powerpc/include/uapi/asm/cputable.h
> +++ b/arch/powerpc/include/uapi/asm/cputable.h
> @@ -1,6 +1,7 @@
> #ifndef _UAPI__ASM_POWERPC_CPUTABLE_H
> #define _UAPI__ASM_POWERPC_CPUTABLE_H
>
> +/* in AT_HWCAP */
> #define PPC_FEATURE_32 0x80000000
> #define PPC_FEATURE_64 0x40000000
> #define PPC_FEATURE_601_INSTR 0x20000000
> @@ -33,4 +34,11 @@
> #define PPC_FEATURE_TRUE_LE 0x00000002
> #define PPC_FEATURE_PPC_LE 0x00000001
>
> +/* in AT_HWCAP2 */
> +#define PPC_FEATURE2_ARCH_2_07 0x80000000
> +#define PPC_FEATURE2_HTM 0x40000000
> +#define PPC_FEATURE2_DSCR 0x20000000
> +#define PPC_FEATURE2_EBB 0x10000000
> +#define PPC_FEATURE2_ISEL 0x08000000
> +
> #endif /* _UAPI__ASM_POWERPC_CPUTABLE_H */
> diff --git a/arch/powerpc/kernel/cputable.c b/arch/powerpc/kernel/cputable.c
> index ae9f433..871c741 100644
> --- a/arch/powerpc/kernel/cputable.c
> +++ b/arch/powerpc/kernel/cputable.c
> @@ -102,6 +102,9 @@ extern void __restore_cpu_e6500(void);
> PPC_FEATURE_SMT | PPC_FEATURE_ICACHE_SNOOP | \
> PPC_FEATURE_TRUE_LE | \
> PPC_FEATURE_PSERIES_PERFMON_COMPAT)
> +#define COMMON_USER2_POWER8 (PPC_FEATURE2_ARCH_2_07 | PPC_FEATURE2_HTM | \
> + PPC_FEATURE2_DSCR | PPC_FEATURE2_EBB | \
> + PPC_FEATURE2_ISEL)
> #define COMMON_USER_PA6T (COMMON_USER_PPC64 | PPC_FEATURE_PA6T |\
> PPC_FEATURE_TRUE_LE | \
> PPC_FEATURE_HAS_ALTIVEC_COMP)
> @@ -443,6 +446,7 @@ static struct cpu_spec __initdata cpu_specs[] = {
> .cpu_name = "POWER8 (architected)",
> .cpu_features = CPU_FTRS_POWER8,
> .cpu_user_features = COMMON_USER_POWER8,
> + .cpu_user_features2 = COMMON_USER2_POWER8,
> .mmu_features = MMU_FTRS_POWER8,
> .icache_bsize = 128,
> .dcache_bsize = 128,
> @@ -492,6 +496,7 @@ static struct cpu_spec __initdata cpu_specs[] = {
> .cpu_name = "POWER8 (raw)",
> .cpu_features = CPU_FTRS_POWER8,
> .cpu_user_features = COMMON_USER_POWER8,
> + .cpu_user_features2 = COMMON_USER2_POWER8,
> .mmu_features = MMU_FTRS_POWER8,
> .icache_bsize = 128,
> .dcache_bsize = 128,
>
^ permalink raw reply [flat|nested] 22+ messages in thread* [PATCH v2 1/4] powerpc/cputable: reserve bits in HWCAP2 for new features
2013-05-04 0:04 ` Michael Neuling
@ 2013-05-04 0:47 ` Nishanth Aravamudan
2013-05-04 0:48 ` [PATCH v2 2/4] powerpc/cputable: advertise DSCR support on P7/P7+ Nishanth Aravamudan
2013-05-06 19:07 ` [PATCH v2 1/4] powerpc/cputable: reserve bits in HWCAP2 for new features Ryan Arnold
0 siblings, 2 replies; 22+ messages in thread
From: Nishanth Aravamudan @ 2013-05-04 0:47 UTC (permalink / raw)
To: Michael Neuling
Cc: Michael R Meissner, Steve Munroe, Peter Bergner, Ryan Arnold,
linuxppc-dev
Also, make HTM's presence dependent on the .config option.
Signed-off-by: Nishanth Aravamudan <nacc@us.ibm.com>
---
Changes since v1:
- Add TAR.
- Make HTM config dependent.
diff --git a/arch/powerpc/include/asm/cputable.h b/arch/powerpc/include/asm/cputable.h
index fcc54ad..26807e5 100644
--- a/arch/powerpc/include/asm/cputable.h
+++ b/arch/powerpc/include/asm/cputable.h
@@ -224,8 +224,10 @@ extern const char *powerpc_base_platform;
/* We only set the TM feature if the kernel was compiled with TM supprt */
#ifdef CONFIG_PPC_TRANSACTIONAL_MEM
#define CPU_FTR_TM_COMP CPU_FTR_TM
+#define PPC_FEATURE2_HTM_COMP PPC_FEATURE2_HTM
#else
#define CPU_FTR_TM_COMP 0
+#define PPC_FEATURE2_HTM_COMP 0
#endif
/* We need to mark all pages as being coherent if we're SMP or we have a
diff --git a/arch/powerpc/include/uapi/asm/cputable.h b/arch/powerpc/include/uapi/asm/cputable.h
index ed9dd81..5b76579 100644
--- a/arch/powerpc/include/uapi/asm/cputable.h
+++ b/arch/powerpc/include/uapi/asm/cputable.h
@@ -1,6 +1,7 @@
#ifndef _UAPI__ASM_POWERPC_CPUTABLE_H
#define _UAPI__ASM_POWERPC_CPUTABLE_H
+/* in AT_HWCAP */
#define PPC_FEATURE_32 0x80000000
#define PPC_FEATURE_64 0x40000000
#define PPC_FEATURE_601_INSTR 0x20000000
@@ -33,4 +34,12 @@
#define PPC_FEATURE_TRUE_LE 0x00000002
#define PPC_FEATURE_PPC_LE 0x00000001
+/* in AT_HWCAP2 */
+#define PPC_FEATURE2_ARCH_2_07 0x80000000
+#define PPC_FEATURE2_HTM 0x40000000
+#define PPC_FEATURE2_DSCR 0x20000000
+#define PPC_FEATURE2_EBB 0x10000000
+#define PPC_FEATURE2_ISEL 0x08000000
+#define PPC_FEATURE2_TAR 0x04000000
+
#endif /* _UAPI__ASM_POWERPC_CPUTABLE_H */
^ permalink raw reply related [flat|nested] 22+ messages in thread* [PATCH v2 2/4] powerpc/cputable: advertise DSCR support on P7/P7+
2013-05-04 0:47 ` [PATCH v2 1/4] powerpc/cputable: reserve bits in HWCAP2 for new features Nishanth Aravamudan
@ 2013-05-04 0:48 ` Nishanth Aravamudan
2013-05-04 0:49 ` [PATCH v2 3/4] powerpc/cputable: advertise ISEL support on appropriate embedded processors Nishanth Aravamudan
2013-05-20 15:04 ` [PATCH v2 2/4] powerpc/cputable: advertise DSCR support on P7/P7+ Will Schmidt
2013-05-06 19:07 ` [PATCH v2 1/4] powerpc/cputable: reserve bits in HWCAP2 for new features Ryan Arnold
1 sibling, 2 replies; 22+ messages in thread
From: Nishanth Aravamudan @ 2013-05-04 0:48 UTC (permalink / raw)
To: Michael Neuling
Cc: Michael R Meissner, Steve Munroe, Peter Bergner, Ryan Arnold,
linuxppc-dev
Signed-off-by: Nishanth Aravamudan <nacc@us.ibm.com>
diff --git a/arch/powerpc/kernel/cputable.c b/arch/powerpc/kernel/cputable.c
index ae9f433..a792157 100644
--- a/arch/powerpc/kernel/cputable.c
+++ b/arch/powerpc/kernel/cputable.c
@@ -98,6 +98,7 @@ extern void __restore_cpu_e6500(void);
PPC_FEATURE_SMT | PPC_FEATURE_ICACHE_SNOOP | \
PPC_FEATURE_TRUE_LE | \
PPC_FEATURE_PSERIES_PERFMON_COMPAT)
+#define COMMON_USER2_POWER7 (PPC_FEATURE2_DSCR)
#define COMMON_USER_POWER8 (COMMON_USER_PPC64 | PPC_FEATURE_ARCH_2_06 |\
PPC_FEATURE_SMT | PPC_FEATURE_ICACHE_SNOOP | \
PPC_FEATURE_TRUE_LE | \
@@ -428,6 +429,7 @@ static struct cpu_spec __initdata cpu_specs[] = {
.cpu_name = "POWER7 (architected)",
.cpu_features = CPU_FTRS_POWER7,
.cpu_user_features = COMMON_USER_POWER7,
+ .cpu_user_features2 = COMMON_USER2_POWER7,
.mmu_features = MMU_FTRS_POWER7,
.icache_bsize = 128,
.dcache_bsize = 128,
@@ -458,6 +460,7 @@ static struct cpu_spec __initdata cpu_specs[] = {
.cpu_name = "POWER7 (raw)",
.cpu_features = CPU_FTRS_POWER7,
.cpu_user_features = COMMON_USER_POWER7,
+ .cpu_user_features2 = COMMON_USER2_POWER7,
.mmu_features = MMU_FTRS_POWER7,
.icache_bsize = 128,
.dcache_bsize = 128,
@@ -475,6 +478,7 @@ static struct cpu_spec __initdata cpu_specs[] = {
.cpu_name = "POWER7+ (raw)",
.cpu_features = CPU_FTRS_POWER7,
.cpu_user_features = COMMON_USER_POWER7,
+ .cpu_user_features = COMMON_USER2_POWER7,
.mmu_features = MMU_FTRS_POWER7,
.icache_bsize = 128,
.dcache_bsize = 128,
^ permalink raw reply related [flat|nested] 22+ messages in thread* [PATCH v2 3/4] powerpc/cputable: advertise ISEL support on appropriate embedded processors
2013-05-04 0:48 ` [PATCH v2 2/4] powerpc/cputable: advertise DSCR support on P7/P7+ Nishanth Aravamudan
@ 2013-05-04 0:49 ` Nishanth Aravamudan
2013-05-04 0:49 ` [PATCH v2 4/4] powerpc/cputable: advertise support for ISEL/HTM/DSCR/TAR on POWER8 Nishanth Aravamudan
2013-05-05 2:01 ` [PATCH v3 3/4] powerpc/cputable: advertise ISEL support on appropriate embedded processors Nishanth Aravamudan
2013-05-20 15:04 ` [PATCH v2 2/4] powerpc/cputable: advertise DSCR support on P7/P7+ Will Schmidt
1 sibling, 2 replies; 22+ messages in thread
From: Nishanth Aravamudan @ 2013-05-04 0:49 UTC (permalink / raw)
To: Michael Neuling
Cc: Michael R Meissner, Steve Munroe, Peter Bergner, Ryan Arnold,
linuxppc-dev
Signed-off-by: Nishanth Aravamudan <nacc@us.ibm.com>
diff --git a/arch/powerpc/kernel/cputable.c b/arch/powerpc/kernel/cputable.c
index a792157..b224cd5 100644
--- a/arch/powerpc/kernel/cputable.c
+++ b/arch/powerpc/kernel/cputable.c
@@ -1999,6 +1999,7 @@ static struct cpu_spec __initdata cpu_specs[] = {
.cpu_user_features = COMMON_USER_BOOKE |
PPC_FEATURE_HAS_SPE_COMP |
PPC_FEATURE_HAS_EFP_SINGLE_COMP,
+ .cpu_user_features2 = PPC_FEATURE2_ISEL,
.mmu_features = MMU_FTR_TYPE_FSL_E,
.icache_bsize = 32,
.dcache_bsize = 32,
@@ -2018,6 +2019,7 @@ static struct cpu_spec __initdata cpu_specs[] = {
PPC_FEATURE_HAS_SPE_COMP |
PPC_FEATURE_HAS_EFP_SINGLE_COMP |
PPC_FEATURE_HAS_EFP_DOUBLE_COMP,
+ .cpu_user_features2 = PPC_FEATURE2_ISEL,
.mmu_features = MMU_FTR_TYPE_FSL_E | MMU_FTR_BIG_PHYS,
.icache_bsize = 32,
.dcache_bsize = 32,
@@ -2034,6 +2036,7 @@ static struct cpu_spec __initdata cpu_specs[] = {
.cpu_name = "e500mc",
.cpu_features = CPU_FTRS_E500MC,
.cpu_user_features = COMMON_USER_BOOKE | PPC_FEATURE_HAS_FPU,
+ .cpu_user_features2 = PPC_FEATURE2_ISEL,
.mmu_features = MMU_FTR_TYPE_FSL_E | MMU_FTR_BIG_PHYS |
MMU_FTR_USE_TLBILX,
.icache_bsize = 64,
@@ -2073,6 +2076,7 @@ static struct cpu_spec __initdata cpu_specs[] = {
.cpu_features = CPU_FTRS_E6500,
.cpu_user_features = COMMON_USER_BOOKE | PPC_FEATURE_HAS_FPU |
PPC_FEATURE_HAS_ALTIVEC_COMP,
+ .cpu_user_features2 = PPC_FEATURE2_ISEL,
.mmu_features = MMU_FTR_TYPE_FSL_E | MMU_FTR_BIG_PHYS |
MMU_FTR_USE_TLBILX,
.icache_bsize = 64,
^ permalink raw reply related [flat|nested] 22+ messages in thread* [PATCH v2 4/4] powerpc/cputable: advertise support for ISEL/HTM/DSCR/TAR on POWER8
2013-05-04 0:49 ` [PATCH v2 3/4] powerpc/cputable: advertise ISEL support on appropriate embedded processors Nishanth Aravamudan
@ 2013-05-04 0:49 ` Nishanth Aravamudan
2013-05-05 2:01 ` [PATCH v3 3/4] powerpc/cputable: advertise ISEL support on appropriate embedded processors Nishanth Aravamudan
1 sibling, 0 replies; 22+ messages in thread
From: Nishanth Aravamudan @ 2013-05-04 0:49 UTC (permalink / raw)
To: Michael Neuling
Cc: Michael R Meissner, Steve Munroe, Peter Bergner, Ryan Arnold,
linuxppc-dev
Signed-off-by: Nishanth Aravamudan <nacc@us.ibm.com>
---
Changes since v1:
- Add TAR.
- Use config dependent symbol for HTM.
diff --git a/arch/powerpc/kernel/cputable.c b/arch/powerpc/kernel/cputable.c
index b224cd5..79cde71 100644
--- a/arch/powerpc/kernel/cputable.c
+++ b/arch/powerpc/kernel/cputable.c
@@ -103,6 +103,9 @@ extern void __restore_cpu_e6500(void);
PPC_FEATURE_SMT | PPC_FEATURE_ICACHE_SNOOP | \
PPC_FEATURE_TRUE_LE | \
PPC_FEATURE_PSERIES_PERFMON_COMPAT)
+#define COMMON_USER2_POWER8 (PPC_FEATURE2_ARCH_2_07 | \
+ PPC_FEATURE2_HTM_COMP | PPC_FEATURE2_DSCR | \
+ PPC_FEATURE2_ISEL | PPC_FEATURE2_TAR)
#define COMMON_USER_PA6T (COMMON_USER_PPC64 | PPC_FEATURE_PA6T |\
PPC_FEATURE_TRUE_LE | \
PPC_FEATURE_HAS_ALTIVEC_COMP)
@@ -445,6 +448,7 @@ static struct cpu_spec __initdata cpu_specs[] = {
.cpu_name = "POWER8 (architected)",
.cpu_features = CPU_FTRS_POWER8,
.cpu_user_features = COMMON_USER_POWER8,
+ .cpu_user_features2 = COMMON_USER2_POWER8,
.mmu_features = MMU_FTRS_POWER8,
.icache_bsize = 128,
.dcache_bsize = 128,
@@ -496,6 +500,7 @@ static struct cpu_spec __initdata cpu_specs[] = {
.cpu_name = "POWER8 (raw)",
.cpu_features = CPU_FTRS_POWER8,
.cpu_user_features = COMMON_USER_POWER8,
+ .cpu_user_features2 = COMMON_USER2_POWER8,
.mmu_features = MMU_FTRS_POWER8,
.icache_bsize = 128,
.dcache_bsize = 128,
^ permalink raw reply related [flat|nested] 22+ messages in thread* [PATCH v3 3/4] powerpc/cputable: advertise ISEL support on appropriate embedded processors
2013-05-04 0:49 ` [PATCH v2 3/4] powerpc/cputable: advertise ISEL support on appropriate embedded processors Nishanth Aravamudan
2013-05-04 0:49 ` [PATCH v2 4/4] powerpc/cputable: advertise support for ISEL/HTM/DSCR/TAR on POWER8 Nishanth Aravamudan
@ 2013-05-05 2:01 ` Nishanth Aravamudan
1 sibling, 0 replies; 22+ messages in thread
From: Nishanth Aravamudan @ 2013-05-05 2:01 UTC (permalink / raw)
To: Michael Neuling
Cc: Peter Bergner, Ryan Arnold, Michael R Meissner, linuxppc-dev,
Steve Munroe
Signed-off-by: Nishanth Aravamudan <nacc@us.ibm.com>
---
Changes since v2:
- Added e5500 per Segher.
I've not added POWER7 yet, as I'm waiting to confirm with others on
that. I will send it as a follow-up patch if needed.
diff --git a/arch/powerpc/kernel/cputable.c b/arch/powerpc/kernel/cputable.c
index a792157..f724bca 100644
--- a/arch/powerpc/kernel/cputable.c
+++ b/arch/powerpc/kernel/cputable.c
@@ -1999,6 +1999,7 @@ static struct cpu_spec __initdata cpu_specs[] = {
.cpu_user_features = COMMON_USER_BOOKE |
PPC_FEATURE_HAS_SPE_COMP |
PPC_FEATURE_HAS_EFP_SINGLE_COMP,
+ .cpu_user_features2 = PPC_FEATURE2_ISEL,
.mmu_features = MMU_FTR_TYPE_FSL_E,
.icache_bsize = 32,
.dcache_bsize = 32,
@@ -2018,6 +2019,7 @@ static struct cpu_spec __initdata cpu_specs[] = {
PPC_FEATURE_HAS_SPE_COMP |
PPC_FEATURE_HAS_EFP_SINGLE_COMP |
PPC_FEATURE_HAS_EFP_DOUBLE_COMP,
+ .cpu_user_features2 = PPC_FEATURE2_ISEL,
.mmu_features = MMU_FTR_TYPE_FSL_E | MMU_FTR_BIG_PHYS,
.icache_bsize = 32,
.dcache_bsize = 32,
@@ -2034,6 +2036,7 @@ static struct cpu_spec __initdata cpu_specs[] = {
.cpu_name = "e500mc",
.cpu_features = CPU_FTRS_E500MC,
.cpu_user_features = COMMON_USER_BOOKE | PPC_FEATURE_HAS_FPU,
+ .cpu_user_features2 = PPC_FEATURE2_ISEL,
.mmu_features = MMU_FTR_TYPE_FSL_E | MMU_FTR_BIG_PHYS |
MMU_FTR_USE_TLBILX,
.icache_bsize = 64,
@@ -2052,6 +2055,7 @@ static struct cpu_spec __initdata cpu_specs[] = {
.cpu_name = "e5500",
.cpu_features = CPU_FTRS_E5500,
.cpu_user_features = COMMON_USER_BOOKE | PPC_FEATURE_HAS_FPU,
+ .cpu_user_features2 = PPC_FEATURE2_ISEL,
.mmu_features = MMU_FTR_TYPE_FSL_E | MMU_FTR_BIG_PHYS |
MMU_FTR_USE_TLBILX,
.icache_bsize = 64,
@@ -2073,6 +2077,7 @@ static struct cpu_spec __initdata cpu_specs[] = {
.cpu_features = CPU_FTRS_E6500,
.cpu_user_features = COMMON_USER_BOOKE | PPC_FEATURE_HAS_FPU |
PPC_FEATURE_HAS_ALTIVEC_COMP,
+ .cpu_user_features2 = PPC_FEATURE2_ISEL,
.mmu_features = MMU_FTR_TYPE_FSL_E | MMU_FTR_BIG_PHYS |
MMU_FTR_USE_TLBILX,
.icache_bsize = 64,
^ permalink raw reply related [flat|nested] 22+ messages in thread
* Re: [PATCH v2 2/4] powerpc/cputable: advertise DSCR support on P7/P7+
2013-05-04 0:48 ` [PATCH v2 2/4] powerpc/cputable: advertise DSCR support on P7/P7+ Nishanth Aravamudan
2013-05-04 0:49 ` [PATCH v2 3/4] powerpc/cputable: advertise ISEL support on appropriate embedded processors Nishanth Aravamudan
@ 2013-05-20 15:04 ` Will Schmidt
2013-05-20 23:41 ` Michael Neuling
1 sibling, 1 reply; 22+ messages in thread
From: Will Schmidt @ 2013-05-20 15:04 UTC (permalink / raw)
To: Nishanth Aravamudan
Cc: Michael Neuling, Michael R Meissner, Steve Munroe, Peter Bergner,
Ryan Arnold, linuxppc-dev
On Fri, 2013-05-03 at 17:48 -0700, Nishanth Aravamudan wrote:
> Signed-off-by: Nishanth Aravamudan <nacc@us.ibm.com>
>
> diff --git a/arch/powerpc/kernel/cputable.c b/arch/powerpc/kernel/cputable.c
> index ae9f433..a792157 100644
> --- a/arch/powerpc/kernel/cputable.c
> +++ b/arch/powerpc/kernel/cputable.c
> @@ -98,6 +98,7 @@ extern void __restore_cpu_e6500(void);
> PPC_FEATURE_SMT | PPC_FEATURE_ICACHE_SNOOP | \
> PPC_FEATURE_TRUE_LE | \
> PPC_FEATURE_PSERIES_PERFMON_COMPAT)
> +#define COMMON_USER2_POWER7 (PPC_FEATURE2_DSCR)
> #define COMMON_USER_POWER8 (COMMON_USER_PPC64 | PPC_FEATURE_ARCH_2_06 |\
> PPC_FEATURE_SMT | PPC_FEATURE_ICACHE_SNOOP | \
> PPC_FEATURE_TRUE_LE | \
> @@ -428,6 +429,7 @@ static struct cpu_spec __initdata cpu_specs[] = {
> .cpu_name = "POWER7 (architected)",
> .cpu_features = CPU_FTRS_POWER7,
> .cpu_user_features = COMMON_USER_POWER7,
> + .cpu_user_features2 = COMMON_USER2_POWER7,
> .mmu_features = MMU_FTRS_POWER7,
> .icache_bsize = 128,
> .dcache_bsize = 128,
> @@ -458,6 +460,7 @@ static struct cpu_spec __initdata cpu_specs[] = {
> .cpu_name = "POWER7 (raw)",
> .cpu_features = CPU_FTRS_POWER7,
> .cpu_user_features = COMMON_USER_POWER7,
> + .cpu_user_features2 = COMMON_USER2_POWER7,
> .mmu_features = MMU_FTRS_POWER7,
> .icache_bsize = 128,
> .dcache_bsize = 128,
> @@ -475,6 +478,7 @@ static struct cpu_spec __initdata cpu_specs[] = {
> .cpu_name = "POWER7+ (raw)",
> .cpu_features = CPU_FTRS_POWER7,
> .cpu_user_features = COMMON_USER_POWER7,
> + .cpu_user_features = COMMON_USER2_POWER7,
^ Oops here, I think. Please consider applying this on top.
Untested, but seems obvious.
Fix a typo in setting COMMON_USER2_POWER7 bits to .cpu_user_features2
cpu specs table.
Signed-off-by: Will Schmidt <will_schmidt@vnet.ibm.com>
diff --git a/arch/powerpc/kernel/cputable.c
b/arch/powerpc/kernel/cputable.c
index c60bbec..51eecb5 100644
--- a/arch/powerpc/kernel/cputable.c
+++ b/arch/powerpc/kernel/cputable.c
@@ -482,7 +482,7 @@ static struct cpu_spec __initdata cpu_specs[] = {
.cpu_name = "POWER7+ (raw)",
.cpu_features = CPU_FTRS_POWER7,
.cpu_user_features = COMMON_USER_POWER7,
- .cpu_user_features = COMMON_USER2_POWER7,
+ .cpu_user_features2 = COMMON_USER2_POWER7,
.mmu_features = MMU_FTRS_POWER7,
.icache_bsize = 128,
.dcache_bsize = 128,
> .mmu_features = MMU_FTRS_POWER7,
> .icache_bsize = 128,
> .dcache_bsize = 128,
>
> _______________________________________________
> Linuxppc-dev mailing list
> Linuxppc-dev@lists.ozlabs.org
> https://lists.ozlabs.org/listinfo/linuxppc-dev
>
^ permalink raw reply related [flat|nested] 22+ messages in thread* Re: [PATCH v2 2/4] powerpc/cputable: advertise DSCR support on P7/P7+
2013-05-20 15:04 ` [PATCH v2 2/4] powerpc/cputable: advertise DSCR support on P7/P7+ Will Schmidt
@ 2013-05-20 23:41 ` Michael Neuling
0 siblings, 0 replies; 22+ messages in thread
From: Michael Neuling @ 2013-05-20 23:41 UTC (permalink / raw)
To: will_schmidt
Cc: Nishanth Aravamudan, Steve Munroe, Peter Bergner, Ryan Arnold,
linuxppc-dev, Michael R Meissner
Will Schmidt <will_schmidt@vnet.ibm.com> wrote:
> On Fri, 2013-05-03 at 17:48 -0700, Nishanth Aravamudan wrote:
> > Signed-off-by: Nishanth Aravamudan <nacc@us.ibm.com>
> >
> > diff --git a/arch/powerpc/kernel/cputable.c b/arch/powerpc/kernel/cputable.c
> > index ae9f433..a792157 100644
> > --- a/arch/powerpc/kernel/cputable.c
> > +++ b/arch/powerpc/kernel/cputable.c
> > @@ -98,6 +98,7 @@ extern void __restore_cpu_e6500(void);
> > PPC_FEATURE_SMT | PPC_FEATURE_ICACHE_SNOOP | \
> > PPC_FEATURE_TRUE_LE | \
> > PPC_FEATURE_PSERIES_PERFMON_COMPAT)
> > +#define COMMON_USER2_POWER7 (PPC_FEATURE2_DSCR)
> > #define COMMON_USER_POWER8 (COMMON_USER_PPC64 | PPC_FEATURE_ARCH_2_06 |\
> > PPC_FEATURE_SMT | PPC_FEATURE_ICACHE_SNOOP | \
> > PPC_FEATURE_TRUE_LE | \
> > @@ -428,6 +429,7 @@ static struct cpu_spec __initdata cpu_specs[] = {
> > .cpu_name = "POWER7 (architected)",
> > .cpu_features = CPU_FTRS_POWER7,
> > .cpu_user_features = COMMON_USER_POWER7,
> > + .cpu_user_features2 = COMMON_USER2_POWER7,
> > .mmu_features = MMU_FTRS_POWER7,
> > .icache_bsize = 128,
> > .dcache_bsize = 128,
> > @@ -458,6 +460,7 @@ static struct cpu_spec __initdata cpu_specs[] = {
> > .cpu_name = "POWER7 (raw)",
> > .cpu_features = CPU_FTRS_POWER7,
> > .cpu_user_features = COMMON_USER_POWER7,
> > + .cpu_user_features2 = COMMON_USER2_POWER7,
> > .mmu_features = MMU_FTRS_POWER7,
> > .icache_bsize = 128,
> > .dcache_bsize = 128,
> > @@ -475,6 +478,7 @@ static struct cpu_spec __initdata cpu_specs[] = {
> > .cpu_name = "POWER7+ (raw)",
> > .cpu_features = CPU_FTRS_POWER7,
> > .cpu_user_features = COMMON_USER_POWER7,
> > + .cpu_user_features = COMMON_USER2_POWER7,
>
> ^ Oops here, I think. Please consider applying this on top.
> Untested, but seems obvious.
>
> Fix a typo in setting COMMON_USER2_POWER7 bits to .cpu_user_features2
> cpu specs table.
Nice catch. Thanks
Acked-by: Michael Neuling <mikey@neuling.org>
>
> Signed-off-by: Will Schmidt <will_schmidt@vnet.ibm.com>
>
>
> diff --git a/arch/powerpc/kernel/cputable.c
> b/arch/powerpc/kernel/cputable.c
> index c60bbec..51eecb5 100644
> --- a/arch/powerpc/kernel/cputable.c
> +++ b/arch/powerpc/kernel/cputable.c
> @@ -482,7 +482,7 @@ static struct cpu_spec __initdata cpu_specs[] = {
> .cpu_name = "POWER7+ (raw)",
> .cpu_features = CPU_FTRS_POWER7,
> .cpu_user_features = COMMON_USER_POWER7,
> - .cpu_user_features = COMMON_USER2_POWER7,
> + .cpu_user_features2 = COMMON_USER2_POWER7,
> .mmu_features = MMU_FTRS_POWER7,
> .icache_bsize = 128,
> .dcache_bsize = 128,
>
>
>
>
>
>
>
>
>
>
>
>
>
>
>
>
>
> > .mmu_features = MMU_FTRS_POWER7,
> > .icache_bsize = 128,
> > .dcache_bsize = 128,
> >
> > _______________________________________________
> > Linuxppc-dev mailing list
> > Linuxppc-dev@lists.ozlabs.org
> > https://lists.ozlabs.org/listinfo/linuxppc-dev
> >
>
>
^ permalink raw reply [flat|nested] 22+ messages in thread
* Re: [PATCH v2 1/4] powerpc/cputable: reserve bits in HWCAP2 for new features
2013-05-04 0:47 ` [PATCH v2 1/4] powerpc/cputable: reserve bits in HWCAP2 for new features Nishanth Aravamudan
2013-05-04 0:48 ` [PATCH v2 2/4] powerpc/cputable: advertise DSCR support on P7/P7+ Nishanth Aravamudan
@ 2013-05-06 19:07 ` Ryan Arnold
2013-05-06 21:41 ` Benjamin Herrenschmidt
1 sibling, 1 reply; 22+ messages in thread
From: Ryan Arnold @ 2013-05-06 19:07 UTC (permalink / raw)
To: Nishanth Aravamudan
Cc: Michael Neuling, Michael R Meissner, Steve Munroe, Peter Bergner,
linuxppc-dev
[-- Attachment #1: Type: text/plain, Size: 939 bytes --]
Hi Nish,
Nishanth Aravamudan <nacc@linux.vnet.ibm.com> wrote on 05/03/2013 07:47:56
PM:
> +/* in AT_HWCAP2 */
> +#define PPC_FEATURE2_ARCH_2_07 0x80000000
> +#define PPC_FEATURE2_HTM 0x40000000
> +#define PPC_FEATURE2_DSCR 0x20000000
> +#define PPC_FEATURE2_EBB 0x10000000
> +#define PPC_FEATURE2_ISEL 0x08000000
> +#define PPC_FEATURE2_TAR 0x04000000
> +
> #endif /* _UAPI__ASM_POWERPC_CPUTABLE_H */
Following the existing naming convention in cputable.h, the features should
probably be amended to the following:
#define PPC_FEATURE2_ARCH_2_07 0x80000000
#define PPC_FEATURE2_HAS_HTM 0x40000000
#define PPC_FEATURE2_HAS_DSC 0x20000000
#define PPC_FEATURE2_HAS_EBB 0x10000000
#define PPC_FEATURE2_HAS_ISEL 0x08000000
#define PPC_FEATURE2_HAS_TAR 0x04000000
Notice that I changed DSCR to DSC. The 'R' wasn't descriptive.
Ryan S. Arnold
IBM Linux Technology Center
[-- Attachment #2: Type: text/html, Size: 1690 bytes --]
^ permalink raw reply [flat|nested] 22+ messages in thread
* Re: [PATCH v2 1/4] powerpc/cputable: reserve bits in HWCAP2 for new features
2013-05-06 19:07 ` [PATCH v2 1/4] powerpc/cputable: reserve bits in HWCAP2 for new features Ryan Arnold
@ 2013-05-06 21:41 ` Benjamin Herrenschmidt
2013-05-07 15:07 ` Ryan Arnold
0 siblings, 1 reply; 22+ messages in thread
From: Benjamin Herrenschmidt @ 2013-05-06 21:41 UTC (permalink / raw)
To: Ryan Arnold
Cc: Michael Neuling, Nishanth Aravamudan, Steve Munroe, Peter Bergner,
linuxppc-dev, Michael R Meissner
On Mon, 2013-05-06 at 14:07 -0500, Ryan Arnold wrote:
> Notice that I changed DSCR to DSC. The 'R' wasn't descriptive.
The "R" is the name of the register for which we are exposing the
availability to userspace... it's also the name of the sysfs entry so
I'd rather keep it for consistency.
Cheers,
Ben.
^ permalink raw reply [flat|nested] 22+ messages in thread
* Re: [PATCH v2 1/4] powerpc/cputable: reserve bits in HWCAP2 for new features
2013-05-06 21:41 ` Benjamin Herrenschmidt
@ 2013-05-07 15:07 ` Ryan Arnold
0 siblings, 0 replies; 22+ messages in thread
From: Ryan Arnold @ 2013-05-07 15:07 UTC (permalink / raw)
To: Benjamin Herrenschmidt
Cc: Michael Neuling, Nishanth Aravamudan, Steve Munroe, Peter Bergner,
linuxppc-dev, Michael R Meissner
[-- Attachment #1: Type: text/plain, Size: 938 bytes --]
Benjamin Herrenschmidt <benh@kernel.crashing.org> wrote on 05/06/2013
04:41:01 PM:
> Benjamin Herrenschmidt <benh@kernel.crashing.org>
> 05/06/2013 04:41 PM
>
> To
>
> Ryan Arnold/Rochester/IBM@IBMUS
>
> cc
>
> Nishanth Aravamudan <nacc@linux.vnet.ibm.com>, linuxppc-
> dev@lists.ozlabs.org, michael@ellerman.id.au, Michael R Meissner/
> Cambridge/IBM@IBMUS, Michael Neuling <mikey@neuling.org>, Peter
> Bergner/Rochester/IBM@IBMUS, Steve Munroe/Rochester/IBM@IBMUS
>
> Subject
>
> Re: [PATCH v2 1/4] powerpc/cputable: reserve bits in HWCAP2 for new
features
>
> On Mon, 2013-05-06 at 14:07 -0500, Ryan Arnold wrote:
> > Notice that I changed DSCR to DSC. The 'R' wasn't descriptive.
>
> The "R" is the name of the register for which we are exposing the
> availability to userspace... it's also the name of the sysfs entry so
> I'd rather keep it for consistency.
I'm fine with keeping the 'R' in the name. Thanks for the input.
Ryan
[-- Attachment #2: Type: text/html, Size: 1554 bytes --]
^ permalink raw reply [flat|nested] 22+ messages in thread