Re: Inbound PCI and Memory Corruption

[Gerhard Sittig <gsi@denx.de>]

On Thu, Jul 18, 2013 at 14:30 -0700, Peter LaDow wrote:
> 
> We are still stumped on this one, but during a review of the system
> setup one thing came up that we aren't sure about is the device tree
> and the DMA engine.
> 
> It does seem that for incoming PCI transactions the Freescale DMA
> engine is not used.  And in our device tree we have the DMA engine
> commented out.  That is, the "fsl,mpc8349-dma" and "fsl,elo-dma"
> compatible items are not present in the FDT.
> 
> I don't suppose this could be a problem?

Can't tell whether it helps or whether I'm telling you what's
already known, but here we go:

Some Freescale SoC's don't have "_the_ DMA", but instead several
of them.  Many peripherals have a DMA engine of their own, which
you won't notice as a separate entity from the software POV
(typically ethernet, USB, PCI, partially video in and out, even
coprocessor may have dedicated DMA engines which they might take
care of themselves).

The thing that you do see (in the device tree, as a software
controllable entity) is the "general purpose DMA" with user
servicable channels.  This one is may be used for serial
communication via UART or SPI, or SDHC/MMC, or peripherals
attached to the EMB.  Sometimes it's called "DMA2" to reflect
that there are others as well.

So:  No, not having to fiddle with DMA stuff when doing PCI need
not be a problem, it's actually expected.  But since a DMA engine
might be involved (that's just not under your command), the
accompanying problems may arise.  You may need to flush CPU
provided data upon write before telling an external entity to
access it, and may need to invalidate caches (to have data
re-fetched) before the CPU accesses what an external entity did
manipulate.  And this applies to both payload data as well as
management data (descriptors) if the latter apply to the former.

HTH


virtually yours
Gerhard Sittig
-- 
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