Re: [RFC] power/mpc85xx: Add delay after enabling I2C master

[Scott Wood <scottwood@freescale.com>]

On Mon, May 13, 2013 at 02:27:08PM -0700, York Sun wrote:
> Erratum A-006037 indicates I2C controller executes the write to I2CCR only
> after it sees SCL idle for 64K cycle of internal I2C controller clocks. If
> during this waiting period, I2C controller is disabled (I2CCR[MEN] set to
> 0), then the controller could end in bad state, and hang the future access
> to I2C register.
> 
> The mpc_i2c_fixup() function tries to recover the bus from a stalled state
> where the 9th clock pulse wasn't generated. However, this workaround
> disables and enables I2C controller without meeting waiting requirement of
> this erratum.
> 
> This erratum applies to some 85xx SoCs. It is safe to apply to all of them
> for mpc_i2c_fixup().
> 
> Signed-off-by: York Sun <yorksun@freescale.com>
> 
> ---
> I'd like to get rid of the #ifdef if mpc5121 is OK with the longer delay.

Are mpc5121 and mpc85xx the only things that use this?

Are you sure the delay always works out to be longer?  What is the
relationship between fsl_get_sys_freq() and i2c->real_clk?

In any case, you should send this patch to the i2c maintainer and list.

-Scott