From: David Miller <davem@davemloft.net>
To: claudiu.manoil@freescale.com
Cc: netdev@vger.kernel.org, linuxppc-dev@lists.ozlabs.org
Subject: Re: [PATCH 1/3] gianfar: Enable eTSEC-A002 erratum w/a for all parts
Date: Wed, 09 Oct 2013 14:02:44 -0400 (EDT) [thread overview]
Message-ID: <20131009.140244.1085107412533674383.davem@davemloft.net> (raw)
In-Reply-To: <1381339242-32030-1-git-send-email-claudiu.manoil@freescale.com>
From: Claudiu Manoil <claudiu.manoil@freescale.com>
Date: Wed, 9 Oct 2013 20:20:40 +0300
> A002 is still in "no plans to fix" state, and applies to all
> the current P1/P2 parts as well, so it's resonable to enable
> its workaround by default, for all the soc's with etsec.
> The impact of not enabling this workaround for affected parts
> is that under certain conditons (runt frames or even frames
> with RX error detected at PHY level) during controller reset,
> the controller might fail to indicate Rx reset (GRS) completion.
>
> Signed-off-by: Claudiu Manoil <claudiu.manoil@freescale.com>
Applied.
prev parent reply other threads:[~2013-10-09 18:02 UTC|newest]
Thread overview: 7+ messages / expand[flat|nested] mbox.gz Atom feed top
2013-10-09 17:20 [PATCH 1/3] gianfar: Enable eTSEC-A002 erratum w/a for all parts Claudiu Manoil
2013-10-09 17:20 ` [PATCH 2/3] gianfar: Use mpc85xx support for errata detection Claudiu Manoil
2013-10-09 18:02 ` David Miller
2013-10-09 20:14 ` Scott Wood
2013-10-09 17:20 ` [PATCH 3/3] gianfar: Enable eTSEC-20 erratum w/a for P2020 Rev1 Claudiu Manoil
2013-10-09 18:02 ` David Miller
2013-10-09 18:02 ` David Miller [this message]
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