From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from merlin.infradead.org (merlin.infradead.org [205.233.59.134]) (using TLSv1.2 with cipher DHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (Client did not present a certificate) by ozlabs.org (Postfix) with ESMTPS id CAC452C009C for ; Wed, 6 Nov 2013 05:52:20 +1100 (EST) Date: Tue, 5 Nov 2013 19:49:43 +0100 From: Peter Zijlstra To: Will Deacon Subject: Re: [RFC] arch: Introduce new TSO memory barrier smp_tmb() Message-ID: <20131105184943.GY16117@laptop.programming.kicks-ass.net> References: <20131103200124.GK19466@laptop.lan> <20131103224242.GF3947@linux.vnet.ibm.com> <20131104105059.GL3947@linux.vnet.ibm.com> <20131104112254.GK28601@twins.programming.kicks-ass.net> <20131104162732.GN3947@linux.vnet.ibm.com> <20131104191127.GW16117@laptop.programming.kicks-ass.net> <20131104205344.GW3947@linux.vnet.ibm.com> <20131105140548.GD26895@mudshark.cambridge.arm.com> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii In-Reply-To: <20131105140548.GD26895@mudshark.cambridge.arm.com> Cc: Michael Neuling , Mathieu Desnoyers , "heiko.carstens@de.ibm.com" , Oleg Nesterov , LKML , Linux PPC dev , Anton Blanchard , Frederic Weisbecker , Victor Kaplansky , "linux@arm.linux.org.uk" , "Paul E. McKenney" , Linus Torvalds , "schwidefsky@de.ibm.com" List-Id: Linux on PowerPC Developers Mail List List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , On Tue, Nov 05, 2013 at 02:05:48PM +0000, Will Deacon wrote: > > > + > > > +#define smp_store_release(p, v) \ > > > +do { \ > > > + smp_mb(); \ > > > + ACCESS_ONCE(p) = (v); \ > > > +} while (0) > > > + > > > +#define smp_load_acquire(p, v) \ > > > +do { \ > > > + typeof(p) ___p1 = ACCESS_ONCE(p); \ > > > + smp_mb(); \ > > > + return ___p1; \ > > > +} while (0) > > What data sizes do these accessors operate on? Assuming that we want > single-copy atomicity (with respect to interrupts in the UP case), we > probably want a check to stop people passing in things like structs. Fair enough; I think we should restrict to native word sizes same as we do for atomics. Something like so perhaps: #ifdef CONFIG_64BIT #define __check_native_word(t) (sizeof(t) == 4 || sizeof(t) == 8) #else #define __check_native_word(t) (sizeof(t) == 4) #endif #define smp_store_release(p, v) \ do { \ BUILD_BUG_ON(!__check_native_word(p)); \ smp_mb(); \ ACCESS_ONCE(p) = (v); \ } while (0) > > > +#define smp_store_release(p, v) \ > > > +do { \ > > > + asm volatile ("stlr %w0 [%1]" : : "r" (v), "r" (&p) : "memory");\ > > Missing comma between the operands. Also, that 'w' output modifier enforces > a 32-bit store (same early question about sizes). Finally, it might be more > efficient to use "=Q" for the addressing mode, rather than take the address > of p manually. so something like: asm volatile ("stlr %0, [%1]" : : "r" (v), "=Q" (p) : "memory"); ? My inline asm foo is horrid and I mostly get by with copy paste from a semi similar existing form :/ > Random other question: have you considered how these accessors should behave > when presented with __iomem pointers? A what? ;-)