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Date: Tue, 7 Jan 2014 18:21:15 -0600
From: Scott Wood <scottwood@freescale.com>
To: tang yuantian <Yuantian.Tang@freescale.com>
Subject: Re: [v7] clk: corenet: Adds the clock binding
Message-ID: <20140108002115.GA19801@home.buserror.net>
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Cc: mark.rutland@arm.com, devicetree@vger.kernel.org,
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On Wed, Nov 20, 2013 at 05:04:49PM +0800, tang yuantian wrote:
> +Recommended properties:
> +- ranges: Allows valid translation between child's address space and
> +	parent's. Must be present if the device has sub-nodes.
> +- #address-cells: Specifies the number of cells used to represent
> +	physical base addresses.  Must be present if the device has
> +	sub-nodes and set to 1 if present
> +- #size-cells: Specifies the number of cells used to represent
> +	the size of an address. Must be present if the device has
> +	sub-nodes and set to 1 if present

Why are we specifying #address-cells/#size-cells here?

> +2. Clock Provider/Consumer Binding
> +
> +Most of the bindings are from the common clock binding[1].
> + [1] Documentation/devicetree/bindings/clock/clock-bindings.txt
> +
> +Required properties:
> +- compatible : Should include one of the following:
> +	* "fsl,qoriq-core-pll-1.0" for core PLL clocks (v1.0)
> +    * "fsl,qoriq-core-pll-2.0" for core PLL clocks (v2.0)
> +    * "fsl,qoriq-core-mux-1.0" for core mux clocks (v1.0)
> +    * "fsl,qoriq-core-mux-2.0" for core mux clocks (v2.0)
> +	* "fsl,qoriq-sysclk-1.0": for input system clock (v1.0)
> +	* "fsl,qoriq-sysclk-2.0": for input system clock (v2.0)

Some of those lines use tabs and others spaces -- I can fix when applying.

-Scott