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 for <linuxppc-dev@lists.ozlabs.org>; Fri,  4 Apr 2014 21:05:59 +1100 (EST)
Date: Fri, 4 Apr 2014 11:05:32 +0100
From: Mark Brown <broonie@kernel.org>
To: Nicolin Chen <Guangyu.Chen@freescale.com>
Message-ID: <20140404100532.GN14763@sirena.org.uk>
References: <1396595387-4371-1-git-send-email-Guangyu.Chen@freescale.com>
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Subject: Re: [PATCH] ASoC: fsl_sai: Fix Bit Clock Polarity configurations
Cc: alsa-devel@alsa-project.org, Li.Xiubo@freescale.com,
 linuxppc-dev@lists.ozlabs.org, linux-kernel@vger.kernel.org, timur@tabi.org
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On Fri, Apr 04, 2014 at 03:09:47PM +0800, Nicolin Chen wrote:
> The BCP bit in TCR4/RCR4 register rules as followings:
>   0 Bit clock is active high with drive outputs on rising edge
>     and sample inputs on falling edge.
>   1 Bit clock is active low with drive outputs on falling edge
>     and sample inputs on rising edge.

Applied, thanks.

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