From: Shawn Guo <shawn.guo@freescale.com>
To: Nicolin Chen <nicoleotsuka@gmail.com>
Cc: Shengjiu Wang <shengjiu.wang@freescale.com>,
alsa-devel@alsa-project.org, lgirdwood@gmail.com, tiwai@suse.de,
linux-kernel@vger.kernel.org, broonie@kernel.org, timur@tabi.org,
perex@perex.cz, Li.Xiubo@freescale.com,
linuxppc-dev@lists.ozlabs.org
Subject: Re: [PATCH] ASoC: fsl_spdif: don't change the root clock rate of spdif in driver
Date: Wed, 17 Sep 2014 10:31:28 +0800 [thread overview]
Message-ID: <20140917023127.GA16456@dragon> (raw)
In-Reply-To: <20140917022440.GA3216@Asurada>
On Tue, Sep 16, 2014 at 07:24:40PM -0700, Nicolin Chen wrote:
> It's not supported in the clock API or just not implemented in our
> code? Can we just register a clock without CLK_SET_RATE_PARENT to
> achieve the purpose? (We are just trying to fix those PRED and PODF
> dividers when the driver calls set_rate to their GATE clock.)
It seems I misunderstood your question. Yes, if we drop flag
CLK_SET_RATE_PARENT for the gate clock in question, the rate change
request will not be propagated to upstream dividers.
Shawn
next prev parent reply other threads:[~2014-09-17 2:46 UTC|newest]
Thread overview: 7+ messages / expand[flat|nested] mbox.gz Atom feed top
2014-09-16 11:46 [PATCH] ASoC: fsl_spdif: don't change the root clock rate of spdif in driver Shengjiu Wang
2014-09-16 18:19 ` Nicolin Chen
2014-09-16 18:32 ` Mark Brown
2014-09-17 1:32 ` Shawn Guo
2014-09-17 2:24 ` Nicolin Chen
2014-09-17 2:31 ` Shawn Guo [this message]
2014-09-17 2:50 ` Nicolin Chen
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