Re: [POWERPC] 4xx: EP405 boards support for arch/powerpc

[Wolfgang Denk <wd@denx.de>]

Dear Ben,

In message <1413802359.18300.7.camel@pasglop> you wrote:
>
> Ah, I even forgot I wrote that ... I'll have to dig out the docs of
> that chip, maybe later this week. Thanks !
...
> >    565          cbdv = ((pllmr & 0x00060000) >> 17) + 1; /* CPU:PLB */
> >    566          opdv = ((pllmr & 0x00018000) >> 15) + 1; /* PLB:OPB */
> >    567          ppdv = ((pllmr & 0x00001800) >> 13) + 1; /* PLB:PCI */
> >                          ^^^^^^^^^^^^^^^^^^^^^^^^^
> > This mask and shift means that ppdv is always 1.

See 7.7.1 PLL Mode Register (CPC0_PLLMR) page 7.10f:

Bits 17:18 PPDV PCI­PLB Frequency Divisor

So that should be (... & 0x00006000) >> 13 ?

Best regards,

Wolfgang Denk

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