Re: [V4] powerpc, xmon: Enable HW instruction breakpoint on POWER8

[Michael Ellerman <mpe@ellerman.id.au>]

On Fri, 2014-28-11 at 04:36:42 UTC, Anshuman Khandual wrote:
> This patch enables support for hardware instruction breakpoint in
> xmon on POWER8 platform with the help of a new register called the
> CIABR (Completed Instruction Address Breakpoint Register). With this
> patch, a single hardware instruction breakpoint can be added and
> cleared during any active xmon debug session. The hardware based
> instruction breakpoint mechanism works correctly with the existing
> TRAP based instruction breakpoint available on xmon.
> 
> There are no powerpc CPU with CPU_FTR_IABR feature any more. This
> patch has re-purposed all the existing IABR related code to work
> with CIABR register based HW instruction breakpoint.

OK I think I'm happy with this, I am going to add this to the changelog though:

    This has one odd feature, which is that when we hit a breakpoint xmon
    doesn't tell us we have hit the breakpoint. This is because xmon is
    expecting bp->address == regs->nip. Because CIABR fires on completition
    regs->nip points to the instruction after the breakpoint. We could fix
    that, but it would then confuse other parts of the xmon code which think
    we need to emulate the instruction. [mpe]

cheers