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Date: Wed, 21 Jan 2015 10:53:20 -0800
From: Nicolin Chen <nicoleotsuka@gmail.com>
To: Zidan Wang <zidan.wang@freescale.com>
Subject: Re: [alsa-devel][PATCH 3/3] ASoC: fsl_sai: Add support for Right-J
 mode
Message-ID: <20150121185319.GA4238@Alpha>
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 <1421756480-7055-4-git-send-email-zidan.wang@freescale.com>
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Cc: alsa-devel@alsa-project.org, timur@tabi.org, Xiubo.Lee@gmail.com,
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On Tue, Jan 20, 2015 at 08:21:20PM +0800, Zidan Wang wrote:
> Add Right-J mode and set TCR5 FBT bit to let data right justify.
> 
> Signed-off-by: Zidan Wang <zidan.wang@freescale.com>

> -	if (sai->is_lsb_first)
> +	if (sai->is_lsb_first && sai->is_right_j_mode)
>  		val_cr5 |= FSL_SAI_CR5_FBT(0);

Are you sure that FBT(0) is correct for right justified mode?
Because the original code is using FBT(0) for the lsb_first
situation and it shouldn't be right justified mode as default.

Nicolin