From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from ozlabs.org (ozlabs.org [103.22.144.67]) (using TLSv1.2 with cipher AECDH-AES256-SHA (256/256 bits)) (No client certificate requested) by lists.ozlabs.org (Postfix) with ESMTPS id ABDDE1A028F for ; Wed, 18 Mar 2015 10:51:33 +1100 (AEDT) Received: from e23smtp02.au.ibm.com (e23smtp02.au.ibm.com [202.81.31.144]) (using TLSv1 with cipher DHE-RSA-AES256-SHA (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 820F814011D for ; Wed, 18 Mar 2015 10:51:33 +1100 (AEDT) Received: from /spool/local by e23smtp02.au.ibm.com with IBM ESMTP SMTP Gateway: Authorized Use Only! Violators will be prosecuted for from ; Wed, 18 Mar 2015 09:51:32 +1000 Received: from d23relay09.au.ibm.com (d23relay09.au.ibm.com [9.185.63.181]) by d23dlp01.au.ibm.com (Postfix) with ESMTP id 48B252CE8040 for ; Wed, 18 Mar 2015 10:51:30 +1100 (EST) Received: from d23av03.au.ibm.com (d23av03.au.ibm.com [9.190.234.97]) by d23relay09.au.ibm.com (8.14.9/8.14.9/NCO v10.0) with ESMTP id t2HNpLQX37421188 for ; Wed, 18 Mar 2015 10:51:30 +1100 Received: from d23av03.au.ibm.com (localhost [127.0.0.1]) by d23av03.au.ibm.com (8.14.4/8.14.4/NCO v10.0 AVout) with ESMTP id t2HNotKD029874 for ; Wed, 18 Mar 2015 10:50:56 +1100 Date: Wed, 18 Mar 2015 10:11:57 +1100 From: Gavin Shan To: Alex Williamson Subject: Re: [PATCH v2 2/2] drivers/vfio: Support EEH error injection Message-ID: <20150317231156.GA5147@shangw> Reply-To: Gavin Shan References: <1426489282-16725-1-git-send-email-gwshan@linux.vnet.ibm.com> <1426489282-16725-2-git-send-email-gwshan@linux.vnet.ibm.com> <1426625149.3643.335.camel@redhat.com> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii In-Reply-To: <1426625149.3643.335.camel@redhat.com> Cc: kvm@vger.kernel.org, aik@ozlabs.ru, Gavin Shan , agraf@suse.de, linuxppc-dev@ozlabs.org, david@gibson.dropbear.id.au List-Id: Linux on PowerPC Developers Mail List List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , On Tue, Mar 17, 2015 at 02:45:49PM -0600, Alex Williamson wrote: >On Mon, 2015-03-16 at 18:01 +1100, Gavin Shan wrote: >> The patch adds one more EEH sub-command (VFIO_EEH_PE_INJECT_ERR) >> to inject the specified EEH error, which is represented by >> (struct vfio_eeh_pe_err), to the indicated PE for testing purpose. >> >> Signed-off-by: Gavin Shan >> --- >> v2: Put additional arguments for error injection to union >> --- >> Documentation/vfio.txt | 12 ++++++++++++ >> drivers/vfio/vfio_spapr_eeh.c | 10 ++++++++++ >> include/uapi/linux/vfio.h | 36 +++++++++++++++++++++++++++++++++++- >> 3 files changed, 57 insertions(+), 1 deletion(-) >> >> diff --git a/Documentation/vfio.txt b/Documentation/vfio.txt >> index 96978ec..c6e11a3 100644 >> --- a/Documentation/vfio.txt >> +++ b/Documentation/vfio.txt >> @@ -385,6 +385,18 @@ The code flow from the example above should be slightly changed: >> >> .... >> >> + /* Inject EEH error, which is expected to be caused by 32-bits >> + * config load. >> + */ >> + pe_op.op = VFIO_EEH_PE_INJECT_ERR; >> + pe_op.err.type = VFIO_EEH_ERR_TYPE_32; >> + pe_op.err.func = VFIO_EEH_ERR_FUNC_LD_CFG_ADDR; >> + pe_op.err.addr = 0ul; >> + pe_op.err.mask = 0ul; >> + ioctl(container, VFIO_EEH_PE_OP, &pe_op); >> + >> + .... >> + >> /* When 0xFF's returned from reading PCI config space or IO BARs >> * of the PCI device. Check the PE's state to see if that has been >> * frozen. >> diff --git a/drivers/vfio/vfio_spapr_eeh.c b/drivers/vfio/vfio_spapr_eeh.c >> index 5fa42db..25ca634 100644 >> --- a/drivers/vfio/vfio_spapr_eeh.c >> +++ b/drivers/vfio/vfio_spapr_eeh.c >> @@ -85,6 +85,16 @@ long vfio_spapr_iommu_eeh_ioctl(struct iommu_group *group, >> case VFIO_EEH_PE_CONFIGURE: >> ret = eeh_pe_configure(pe); >> break; >> + case VFIO_EEH_PE_INJECT_ERR: >> + if (op.argsz < sizeof(struct vfio_eeh_pe_op)) > >This will need to be updated if vfio_eeh_pe_op ever gets updated again, >why not just use offsetofend() now and avoid that future hassle and >breakage. > Good point. I'll update to use "minsz = offsetofend(struct vfio_eeh_pe_op, err.mask)", then use "minsz" for the parameter check and memory copy. >> + return -EINVAL; >> + if (copy_from_user(&op, (void __user *)arg, >> + sizeof(struct vfio_eeh_pe_op))) > >And here. > As above. >BTW, please use cover letters > Sure, thanks for review! Thanks, Gavin >> + return -EFAULT; >> + >> + ret = eeh_pe_inject_err(pe, op.err.type, op.err.func, >> + op.err.addr, op.err.mask); >> + break; >> default: >> ret = -EINVAL; >> } >> diff --git a/include/uapi/linux/vfio.h b/include/uapi/linux/vfio.h >> index 82889c3..f68e962 100644 >> --- a/include/uapi/linux/vfio.h >> +++ b/include/uapi/linux/vfio.h >> @@ -468,12 +468,23 @@ struct vfio_iommu_spapr_tce_info { >> * - unfreeze IO/DMA for frozen PE; >> * - read PE state; >> * - reset PE; >> - * - configure PE. >> + * - configure PE; >> + * - inject EEH error. >> */ >> +struct vfio_eeh_pe_err { >> + __u32 type; >> + __u32 func; >> + __u64 addr; >> + __u64 mask; >> +}; >> + >> struct vfio_eeh_pe_op { >> __u32 argsz; >> __u32 flags; >> __u32 op; >> + union { >> + struct vfio_eeh_pe_err err; >> + }; >> }; >> >> #define VFIO_EEH_PE_DISABLE 0 /* Disable EEH functionality */ >> @@ -490,6 +501,29 @@ struct vfio_eeh_pe_op { >> #define VFIO_EEH_PE_RESET_HOT 6 /* Assert hot reset */ >> #define VFIO_EEH_PE_RESET_FUNDAMENTAL 7 /* Assert fundamental reset */ >> #define VFIO_EEH_PE_CONFIGURE 8 /* PE configuration */ >> +#define VFIO_EEH_PE_INJECT_ERR 9 /* Inject EEH error */ >> +#define VFIO_EEH_ERR_TYPE_32 0 /* 32-bits EEH error type */ >> +#define VFIO_EEH_ERR_TYPE_64 1 /* 64-bits EEH error type */ >> +#define VFIO_EEH_ERR_FUNC_LD_MEM_ADDR 0 /* Memory load */ >> +#define VFIO_EEH_ERR_FUNC_LD_MEM_DATA 1 >> +#define VFIO_EEH_ERR_FUNC_LD_IO_ADDR 2 /* IO load */ >> +#define VFIO_EEH_ERR_FUNC_LD_IO_DATA 3 >> +#define VFIO_EEH_ERR_FUNC_LD_CFG_ADDR 4 /* Config load */ >> +#define VFIO_EEH_ERR_FUNC_LD_CFG_DATA 5 >> +#define VFIO_EEH_ERR_FUNC_ST_MEM_ADDR 6 /* Memory store */ >> +#define VFIO_EEH_ERR_FUNC_ST_MEM_DATA 7 >> +#define VFIO_EEH_ERR_FUNC_ST_IO_ADDR 8 /* IO store */ >> +#define VFIO_EEH_ERR_FUNC_ST_IO_DATA 9 >> +#define VFIO_EEH_ERR_FUNC_ST_CFG_ADDR 10 /* Config store */ >> +#define VFIO_EEH_ERR_FUNC_ST_CFG_DATA 11 >> +#define VFIO_EEH_ERR_FUNC_DMA_RD_ADDR 12 /* DMA read */ >> +#define VFIO_EEH_ERR_FUNC_DMA_RD_DATA 13 >> +#define VFIO_EEH_ERR_FUNC_DMA_RD_MASTER 14 >> +#define VFIO_EEH_ERR_FUNC_DMA_RD_TARGET 15 >> +#define VFIO_EEH_ERR_FUNC_DMA_WR_ADDR 16 /* DMA write */ >> +#define VFIO_EEH_ERR_FUNC_DMA_WR_DATA 17 >> +#define VFIO_EEH_ERR_FUNC_DMA_WR_MASTER 18 >> +#define VFIO_EEH_ERR_FUNC_DMA_WR_TARGET 19 >> >> #define VFIO_EEH_PE_OP _IO(VFIO_TYPE, VFIO_BASE + 21) >> > > >