From: Paul Mackerras <paulus@samba.org>
To: Scott Wood <scottwood@freescale.com>
Cc: Sam Bobroff <sam.bobroff@au1.ibm.com>,
kvm-ppc@vger.kernel.org, linuxppc-dev@lists.ozlabs.org,
Mihai Caraman <mihai.caraman@freescale.com>
Subject: Re: [PATCH 1/1] KVM: PPC: Book3S: correct width in XER handling
Date: Thu, 21 May 2015 12:51:09 +1000 [thread overview]
Message-ID: <20150521025109.GA12975@drongo.ozlabs.ibm.com> (raw)
In-Reply-To: <1432161308.27761.116.camel@freescale.com>
On Wed, May 20, 2015 at 05:35:08PM -0500, Scott Wood wrote:
>
> It's nominally a 64-bit register, but the upper 32 bits are reserved in
> ISA 2.06. Do newer ISAs or certain implementations define things in the
> upper 32 bits, or is this just about the asm accesses being wrong on
> big-endian?
It's primarily about the asm accesses being wrong.
Paul.
next prev parent reply other threads:[~2015-05-21 2:51 UTC|newest]
Thread overview: 7+ messages / expand[flat|nested] mbox.gz Atom feed top
2015-05-20 5:26 [PATCH 1/1] KVM: PPC: Book3S: correct width in XER handling Sam Bobroff
2015-05-20 22:26 ` Paul Mackerras
2015-05-20 22:35 ` Scott Wood
2015-05-21 2:51 ` Paul Mackerras [this message]
2015-05-25 21:08 ` Alexander Graf
2015-05-26 0:14 ` Sam Bobroff
2015-05-26 0:23 ` Alexander Graf
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