[PATCH 1/3] powerpc/mm: PTE_RPN_MAX is not used, remove the same

[PATCH 1/3] powerpc/mm: PTE_RPN_MAX is not used, remove the same

[Aneesh Kumar K.V]

Remove the unused #define

Signed-off-by: Aneesh Kumar K.V <aneesh.kumar@linux.vnet.ibm.com>
---
 arch/powerpc/include/asm/pte-common.h | 2 --
 1 file changed, 2 deletions(-)

diff --git a/arch/powerpc/include/asm/pte-common.h b/arch/powerpc/include/asm/pte-common.h
index c5a755ef7011..b7c8d079c121 100644
--- a/arch/powerpc/include/asm/pte-common.h
+++ b/arch/powerpc/include/asm/pte-common.h
@@ -85,10 +85,8 @@ extern unsigned long bad_call_to_PMD_PAGE_SIZE(void);
  * 64-bit PTEs
  */
 #if defined(CONFIG_PPC32) && defined(CONFIG_PTE_64BIT)
-#define PTE_RPN_MAX	(1ULL << (64 - PTE_RPN_SHIFT))
 #define PTE_RPN_MASK	(~((1ULL<<PTE_RPN_SHIFT)-1))
 #else
-#define PTE_RPN_MAX	(1UL << (32 - PTE_RPN_SHIFT))
 #define PTE_RPN_MASK	(~((1UL<<PTE_RPN_SHIFT)-1))
 #endif
 
-- 
2.1.4

[PATCH 2/3] powerpc/mm: Limit the max memory we can support

[Aneesh Kumar K.V]

We need to limit the max memory based on Linux page table format.
For example, with 4K page size we can't support 64TB memory based
on the existing pte format. Add checks to limit memory based
on pte size.

Signed-off-by: Aneesh Kumar K.V <aneesh.kumar@linux.vnet.ibm.com>
---
 arch/powerpc/kernel/prom.c | 22 +++++++++++++++++++---
 1 file changed, 19 insertions(+), 3 deletions(-)

diff --git a/arch/powerpc/kernel/prom.c b/arch/powerpc/kernel/prom.c
index 308c5e15676b..a0108ddde01c 100644
--- a/arch/powerpc/kernel/prom.c
+++ b/arch/powerpc/kernel/prom.c
@@ -698,9 +698,25 @@ void __init early_init_devtree(void *params)
 #endif
 		reserve_crashkernel();
 	early_reserve_mem();
-
-	/* Ensure that total memory size is page-aligned. */
-	limit = ALIGN(memory_limit ?: memblock_phys_mem_size(), PAGE_SIZE);
+	/*
+	 * if not specified limit the memory based on the pfn count that
+	 * we can fit in pte_t. Also ensure that total memory size is
+	 * page-aligned.
+	 */
+	if (!memory_limit) {
+		int bit_count;
+		phys_addr_t pte_mem_limit;
+
+		BUILD_BUG_ON(sizeof(pte_basic_t) > 8);
+		bit_count = (sizeof(pte_basic_t) * 8) - PTE_RPN_SHIFT + PAGE_SHIFT;
+		pte_mem_limit = ~0ULL >> (64 - bit_count);
+		limit = memblock_phys_mem_size();
+		if (limit > pte_mem_limit)
+			limit = pte_mem_limit;
+	} else
+		limit = memory_limit;
+
+	limit = ALIGN(limit, PAGE_SIZE);
 	memblock_enforce_memory_limit(limit);
 
 	memblock_allow_resize();
-- 
2.1.4

[PATCH 3/3] powerpc/mm: Change the swap encoding in pte.

[Aneesh Kumar K.V]

Current swap encoding in pte can't support large pfns
above 4TB. Change the swap encoding such that we put
the swap type in the PTE bits. Also add build checks
to make sure we don't overlap with HPTEFLAGS.

Signed-off-by: Aneesh Kumar K.V <aneesh.kumar@linux.vnet.ibm.com>
---
 arch/powerpc/include/asm/pgtable-ppc64.h | 26 +++++++++++++++++++++-----
 arch/powerpc/include/asm/pte-book3e.h    |  1 +
 arch/powerpc/include/asm/pte-hash64.h    |  1 +
 3 files changed, 23 insertions(+), 5 deletions(-)

diff --git a/arch/powerpc/include/asm/pgtable-ppc64.h b/arch/powerpc/include/asm/pgtable-ppc64.h
index 43e6ad424c7f..954ae1201e42 100644
--- a/arch/powerpc/include/asm/pgtable-ppc64.h
+++ b/arch/powerpc/include/asm/pgtable-ppc64.h
@@ -347,11 +347,27 @@ static inline void __ptep_set_access_flags(pte_t *ptep, pte_t entry)
 	pr_err("%s:%d: bad pgd %08lx.\n", __FILE__, __LINE__, pgd_val(e))
 
 /* Encode and de-code a swap entry */
-#define __swp_type(entry)	(((entry).val >> 1) & 0x3f)
-#define __swp_offset(entry)	((entry).val >> 8)
-#define __swp_entry(type, offset) ((swp_entry_t){((type)<< 1)|((offset)<<8)})
-#define __pte_to_swp_entry(pte)	((swp_entry_t){pte_val(pte) >> PTE_RPN_SHIFT})
-#define __swp_entry_to_pte(x)	((pte_t) { (x).val << PTE_RPN_SHIFT })
+#define MAX_SWAPFILES_CHECK() do { \
+	BUILD_BUG_ON(MAX_SWAPFILES_SHIFT > SWP_TYPE_BITS); \
+	/*							\
+	 * Don't have overlapping bits with _PAGE_HPTEFLAGS	\
+	 * We filter HPTEFLAGS on set_pte.			\
+	 */							\
+	BUILD_BUG_ON(_PAGE_HPTEFLAGS & (0x1f << _PAGE_BIT_SWAP_TYPE)); \
+	} while (0)
+/*
+ * on pte we don't need handle RADIX_TREE_EXCEPTIONAL_SHIFT;
+ */
+#define SWP_TYPE_BITS 5
+#define __swp_type(x)		(((x).val >> _PAGE_BIT_SWAP_TYPE) \
+				& ((1UL << SWP_TYPE_BITS) - 1))
+#define __swp_offset(x)		((x).val >> PTE_RPN_SHIFT)
+#define __swp_entry(type, offset)	((swp_entry_t) { \
+					((type) << _PAGE_BIT_SWAP_TYPE) \
+					| ((offset) << PTE_RPN_SHIFT) })
+
+#define __pte_to_swp_entry(pte)		((swp_entry_t) { pte_val((pte)) })
+#define __swp_entry_to_pte(x)		__pte((x).val)
 
 void pgtable_cache_add(unsigned shift, void (*ctor)(void *));
 void pgtable_cache_init(void);
diff --git a/arch/powerpc/include/asm/pte-book3e.h b/arch/powerpc/include/asm/pte-book3e.h
index 91a704952ca1..8d8473278d91 100644
--- a/arch/powerpc/include/asm/pte-book3e.h
+++ b/arch/powerpc/include/asm/pte-book3e.h
@@ -11,6 +11,7 @@
 /* Architected bits */
 #define _PAGE_PRESENT	0x000001 /* software: pte contains a translation */
 #define _PAGE_SW1	0x000002
+#define _PAGE_BIT_SWAP_TYPE	2
 #define _PAGE_BAP_SR	0x000004
 #define _PAGE_BAP_UR	0x000008
 #define _PAGE_BAP_SW	0x000010
diff --git a/arch/powerpc/include/asm/pte-hash64.h b/arch/powerpc/include/asm/pte-hash64.h
index fc852f7e7b3a..ef612c160da7 100644
--- a/arch/powerpc/include/asm/pte-hash64.h
+++ b/arch/powerpc/include/asm/pte-hash64.h
@@ -16,6 +16,7 @@
  */
 #define _PAGE_PRESENT		0x0001 /* software: pte contains a translation */
 #define _PAGE_USER		0x0002 /* matches one of the PP bits */
+#define _PAGE_BIT_SWAP_TYPE	2
 #define _PAGE_EXEC		0x0004 /* No execute on POWER4 and newer (we invert) */
 #define _PAGE_GUARDED		0x0008
 /* We can derive Memory coherence from _PAGE_NO_CACHE */
-- 
2.1.4

Re: [PATCH 3/3] powerpc/mm: Change the swap encoding in pte.

[Haren Myneni]

Tested this patch on 16TB system and fixed the BUG_ON issue mentioned
here - https://lists.ozlabs.org/pipermail/linuxppc-dev/2015-May/128767.html

I was able to reproduce this issue in all previous releases (tested
from 3.14). So this patch should be also in stable tree.

Acked-by: Haren Myneni <hbabu@us.ibm.com>

On 5/28/15, Aneesh Kumar K.V <aneesh.kumar@linux.vnet.ibm.com> wrote:
> Current swap encoding in pte can't support large pfns
> above 4TB. Change the swap encoding such that we put
> the swap type in the PTE bits. Also add build checks
> to make sure we don't overlap with HPTEFLAGS.
>
> Signed-off-by: Aneesh Kumar K.V <aneesh.kumar@linux.vnet.ibm.com>
> ---
>  arch/powerpc/include/asm/pgtable-ppc64.h | 26 +++++++++++++++++++++-----
>  arch/powerpc/include/asm/pte-book3e.h    |  1 +
>  arch/powerpc/include/asm/pte-hash64.h    |  1 +
>  3 files changed, 23 insertions(+), 5 deletions(-)
>
> diff --git a/arch/powerpc/include/asm/pgtable-ppc64.h
> b/arch/powerpc/include/asm/pgtable-ppc64.h
> index 43e6ad424c7f..954ae1201e42 100644
> --- a/arch/powerpc/include/asm/pgtable-ppc64.h
> +++ b/arch/powerpc/include/asm/pgtable-ppc64.h
> @@ -347,11 +347,27 @@ static inline void __ptep_set_access_flags(pte_t
> *ptep, pte_t entry)
>  	pr_err("%s:%d: bad pgd %08lx.\n", __FILE__, __LINE__, pgd_val(e))
>
>  /* Encode and de-code a swap entry */
> -#define __swp_type(entry)	(((entry).val >> 1) & 0x3f)
> -#define __swp_offset(entry)	((entry).val >> 8)
> -#define __swp_entry(type, offset) ((swp_entry_t){((type)<<
> 1)|((offset)<<8)})
> -#define __pte_to_swp_entry(pte)	((swp_entry_t){pte_val(pte) >>
> PTE_RPN_SHIFT})
> -#define __swp_entry_to_pte(x)	((pte_t) { (x).val << PTE_RPN_SHIFT })
> +#define MAX_SWAPFILES_CHECK() do { \
> +	BUILD_BUG_ON(MAX_SWAPFILES_SHIFT > SWP_TYPE_BITS); \
> +	/*							\
> +	 * Don't have overlapping bits with _PAGE_HPTEFLAGS	\
> +	 * We filter HPTEFLAGS on set_pte.			\
> +	 */							\
> +	BUILD_BUG_ON(_PAGE_HPTEFLAGS & (0x1f << _PAGE_BIT_SWAP_TYPE)); \
> +	} while (0)
> +/*
> + * on pte we don't need handle RADIX_TREE_EXCEPTIONAL_SHIFT;
> + */
> +#define SWP_TYPE_BITS 5
> +#define __swp_type(x)		(((x).val >> _PAGE_BIT_SWAP_TYPE) \
> +				& ((1UL << SWP_TYPE_BITS) - 1))
> +#define __swp_offset(x)		((x).val >> PTE_RPN_SHIFT)
> +#define __swp_entry(type, offset)	((swp_entry_t) { \
> +					((type) << _PAGE_BIT_SWAP_TYPE) \
> +					| ((offset) << PTE_RPN_SHIFT) })
> +
> +#define __pte_to_swp_entry(pte)		((swp_entry_t) { pte_val((pte)) })
> +#define __swp_entry_to_pte(x)		__pte((x).val)
>
>  void pgtable_cache_add(unsigned shift, void (*ctor)(void *));
>  void pgtable_cache_init(void);
> diff --git a/arch/powerpc/include/asm/pte-book3e.h
> b/arch/powerpc/include/asm/pte-book3e.h
> index 91a704952ca1..8d8473278d91 100644
> --- a/arch/powerpc/include/asm/pte-book3e.h
> +++ b/arch/powerpc/include/asm/pte-book3e.h
> @@ -11,6 +11,7 @@
>  /* Architected bits */
>  #define _PAGE_PRESENT	0x000001 /* software: pte contains a translation */
>  #define _PAGE_SW1	0x000002
> +#define _PAGE_BIT_SWAP_TYPE	2
>  #define _PAGE_BAP_SR	0x000004
>  #define _PAGE_BAP_UR	0x000008
>  #define _PAGE_BAP_SW	0x000010
> diff --git a/arch/powerpc/include/asm/pte-hash64.h
> b/arch/powerpc/include/asm/pte-hash64.h
> index fc852f7e7b3a..ef612c160da7 100644
> --- a/arch/powerpc/include/asm/pte-hash64.h
> +++ b/arch/powerpc/include/asm/pte-hash64.h
> @@ -16,6 +16,7 @@
>   */
>  #define _PAGE_PRESENT		0x0001 /* software: pte contains a translation */
>  #define _PAGE_USER		0x0002 /* matches one of the PP bits */
> +#define _PAGE_BIT_SWAP_TYPE	2
>  #define _PAGE_EXEC		0x0004 /* No execute on POWER4 and newer (we invert)
> */
>  #define _PAGE_GUARDED		0x0008
>  /* We can derive Memory coherence from _PAGE_NO_CACHE */
> --
> 2.1.4
>
>

[PATCH V2] powerpc/mm: Limit the max memory we can support

[Aneesh Kumar K.V]

We need to limit the max memory based on Linux page table format.
Add checks to limit memory based on pte size. Also limit the memory
based on MAX_PHSYSMEM_BITS.

Signed-off-by: Aneesh Kumar K.V <aneesh.kumar@linux.vnet.ibm.com>
---
Changes from V1:
* Update commit message. 4K can handle 64TB
* Also limit based on MAX_PHSYSMEM_BITS

 arch/powerpc/include/asm/mmu.h       |  8 ++++++++
 arch/powerpc/include/asm/sparsemem.h |  2 --
 arch/powerpc/kernel/prom.c           | 25 ++++++++++++++++++++++---
 3 files changed, 30 insertions(+), 5 deletions(-)

diff --git a/arch/powerpc/include/asm/mmu.h b/arch/powerpc/include/asm/mmu.h
index 3d5abfe6ba67..d44d49093c8d 100644
--- a/arch/powerpc/include/asm/mmu.h
+++ b/arch/powerpc/include/asm/mmu.h
@@ -200,6 +200,14 @@ static inline void assert_pte_locked(struct mm_struct *mm, unsigned long addr)
 #  include <asm/mmu-8xx.h>
 #endif
 
+#ifdef CONFIG_PHYS_64BIT
+/*
+ * Max supported memory on 64bit system is 64TB.
+ */
+#define MAX_PHYSMEM_BITS        46
+#else
+#define MAX_PHYSMEM_BITS        32
+#endif
 
 #endif /* __KERNEL__ */
 #endif /* _ASM_POWERPC_MMU_H_ */
diff --git a/arch/powerpc/include/asm/sparsemem.h b/arch/powerpc/include/asm/sparsemem.h
index f6fc0ee813d7..fc3808378893 100644
--- a/arch/powerpc/include/asm/sparsemem.h
+++ b/arch/powerpc/include/asm/sparsemem.h
@@ -11,8 +11,6 @@
 #define SECTION_SIZE_BITS       24
 
 #define MAX_PHYSADDR_BITS       46
-#define MAX_PHYSMEM_BITS        46
-
 #endif /* CONFIG_SPARSEMEM */
 
 #ifdef CONFIG_MEMORY_HOTPLUG
diff --git a/arch/powerpc/kernel/prom.c b/arch/powerpc/kernel/prom.c
index 308c5e15676b..c09315b32ca7 100644
--- a/arch/powerpc/kernel/prom.c
+++ b/arch/powerpc/kernel/prom.c
@@ -698,9 +698,28 @@ void __init early_init_devtree(void *params)
 #endif
 		reserve_crashkernel();
 	early_reserve_mem();
-
-	/* Ensure that total memory size is page-aligned. */
-	limit = ALIGN(memory_limit ?: memblock_phys_mem_size(), PAGE_SIZE);
+	/*
+	 * if not specified limit the memory based on the pfn count that
+	 * we can fit in pte_t. Also ensure that total memory size is
+	 * page-aligned.
+	 */
+	if (!memory_limit) {
+		int bit_count;
+		phys_addr_t pte_mem_limit;
+
+		limit = memblock_phys_mem_size();
+		if (limit >= (1ULL << MAX_PHYSMEM_BITS))
+			limit = (1ULL << MAX_PHYSMEM_BITS) - 1;
+
+		BUILD_BUG_ON(sizeof(pte_basic_t) > 8);
+		bit_count = (sizeof(pte_basic_t) * 8) - PTE_RPN_SHIFT + PAGE_SHIFT;
+		pte_mem_limit = ~0ULL >> (64 - bit_count);
+		if (limit > pte_mem_limit)
+			limit = pte_mem_limit;
+	} else
+		limit = memory_limit;
+
+	limit = ALIGN(limit, PAGE_SIZE);
 	memblock_enforce_memory_limit(limit);
 
 	memblock_allow_resize();
-- 
2.1.4

Re: [V2] powerpc/mm: Limit the max memory we can support

[Michael Ellerman]

On Fri, 2015-29-05 at 08:20:18 UTC, "Aneesh Kumar K.V" wrote:
> We need to limit the max memory based on Linux page table format.
> Add checks to limit memory based on pte size. Also limit the memory
> based on MAX_PHSYSMEM_BITS.
> 
> Signed-off-by: Aneesh Kumar K.V <aneesh.kumar@linux.vnet.ibm.com>
> ---
> Changes from V1:
> * Update commit message. 4K can handle 64TB
> * Also limit based on MAX_PHSYSMEM_BITS
> 
>  arch/powerpc/include/asm/mmu.h       |  8 ++++++++
>  arch/powerpc/include/asm/sparsemem.h |  2 --
>  arch/powerpc/kernel/prom.c           | 25 ++++++++++++++++++++++---
>  3 files changed, 30 insertions(+), 5 deletions(-)
> 
> diff --git a/arch/powerpc/include/asm/mmu.h b/arch/powerpc/include/asm/mmu.h
> index 3d5abfe6ba67..d44d49093c8d 100644
> --- a/arch/powerpc/include/asm/mmu.h
> +++ b/arch/powerpc/include/asm/mmu.h
> @@ -200,6 +200,14 @@ static inline void assert_pte_locked(struct mm_struct *mm, unsigned long addr)
>  #  include <asm/mmu-8xx.h>
>  #endif
>  
> +#ifdef CONFIG_PHYS_64BIT
> +/*
> + * Max supported memory on 64bit system is 64TB.

Can you document in the comment where the limit comes from?

> + */
> +#define MAX_PHYSMEM_BITS        46
> +#else
> +#define MAX_PHYSMEM_BITS        32
> +#endif
>  
>  #endif /* __KERNEL__ */
>  #endif /* _ASM_POWERPC_MMU_H_ */
> diff --git a/arch/powerpc/include/asm/sparsemem.h b/arch/powerpc/include/asm/sparsemem.h
> index f6fc0ee813d7..fc3808378893 100644
> --- a/arch/powerpc/include/asm/sparsemem.h
> +++ b/arch/powerpc/include/asm/sparsemem.h
> @@ -11,8 +11,6 @@
>  #define SECTION_SIZE_BITS       24
>  
>  #define MAX_PHYSADDR_BITS       46
> -#define MAX_PHYSMEM_BITS        46

Is there now no link between those two?

>  #ifdef CONFIG_MEMORY_HOTPLUG
> diff --git a/arch/powerpc/kernel/prom.c b/arch/powerpc/kernel/prom.c
> index 308c5e15676b..c09315b32ca7 100644
> --- a/arch/powerpc/kernel/prom.c
> +++ b/arch/powerpc/kernel/prom.c
> @@ -698,9 +698,28 @@ void __init early_init_devtree(void *params)
>  #endif
>  		reserve_crashkernel();
>  	early_reserve_mem();
> -
> -	/* Ensure that total memory size is page-aligned. */
> -	limit = ALIGN(memory_limit ?: memblock_phys_mem_size(), PAGE_SIZE);
> +	/*
> +	 * if not specified limit the memory based on the pfn count that
> +	 * we can fit in pte_t. Also ensure that total memory size is
> +	 * page-aligned.

Shouldn't you do the logic below even if memory_limit is specified? Otherwise
someone can specify a really large memory_limit which will then overflow.

> +	 */
> +	if (!memory_limit) {
> +		int bit_count;
> +		phys_addr_t pte_mem_limit;
> +
> +		limit = memblock_phys_mem_size();
> +		if (limit >= (1ULL << MAX_PHYSMEM_BITS))
> +			limit = (1ULL << MAX_PHYSMEM_BITS) - 1;
> +
> +		BUILD_BUG_ON(sizeof(pte_basic_t) > 8);
> +		bit_count = (sizeof(pte_basic_t) * 8) - PTE_RPN_SHIFT + PAGE_SHIFT;
> +		pte_mem_limit = ~0ULL >> (64 - bit_count);

It's fairly obvious what you're doing here, but a bit of a comment wouldn't hurt.

> +		if (limit > pte_mem_limit)
> +			limit = pte_mem_limit;
> +	} else
> +		limit = memory_limit;
> +
> +	limit = ALIGN(limit, PAGE_SIZE);

cheers

Re: [V2] powerpc/mm: Limit the max memory we can support

[Aneesh Kumar K.V]

Michael Ellerman <mpe@ellerman.id.au> writes:

> On Fri, 2015-29-05 at 08:20:18 UTC, "Aneesh Kumar K.V" wrote:
>> We need to limit the max memory based on Linux page table format.
>> Add checks to limit memory based on pte size. Also limit the memory
>> based on MAX_PHSYSMEM_BITS.
>> 
>> Signed-off-by: Aneesh Kumar K.V <aneesh.kumar@linux.vnet.ibm.com>
>> ---
>> Changes from V1:
>> * Update commit message. 4K can handle 64TB
>> * Also limit based on MAX_PHSYSMEM_BITS
>> 
>>  arch/powerpc/include/asm/mmu.h       |  8 ++++++++
>>  arch/powerpc/include/asm/sparsemem.h |  2 --
>>  arch/powerpc/kernel/prom.c           | 25 ++++++++++++++++++++++---
>>  3 files changed, 30 insertions(+), 5 deletions(-)
>> 
>> diff --git a/arch/powerpc/include/asm/mmu.h b/arch/powerpc/include/asm/mmu.h
>> index 3d5abfe6ba67..d44d49093c8d 100644
>> --- a/arch/powerpc/include/asm/mmu.h
>> +++ b/arch/powerpc/include/asm/mmu.h
>> @@ -200,6 +200,14 @@ static inline void assert_pte_locked(struct mm_struct *mm, unsigned long addr)
>>  #  include <asm/mmu-8xx.h>
>>  #endif
>>  
>> +#ifdef CONFIG_PHYS_64BIT
>> +/*
>> + * Max supported memory on 64bit system is 64TB.
>
> Can you document in the comment where the limit comes from?

Will update the patch addressing all your feedback. But I would request
to drop this patch from the series for now. We need further fixes [1] in
this area and I will do a separate series addressing all the issues.

[1] Right now we ALIGN the total memory with PAGE_SIZE. That is not
really correct if we end up doing kernel linear mapping with 16MB size. 

>
>> + */
>> +#define MAX_PHYSMEM_BITS        46
>> +#else
>> +#define MAX_PHYSMEM_BITS        32
>> +#endif
>>  
>>  #endif /* __KERNEL__ */
>>  #endif /* _ASM_POWERPC_MMU_H_ */
>> diff --git a/arch/powerpc/include/asm/sparsemem.h b/arch/powerpc/include/asm/sparsemem.h
>> index f6fc0ee813d7..fc3808378893 100644
>> --- a/arch/powerpc/include/asm/sparsemem.h
>> +++ b/arch/powerpc/include/asm/sparsemem.h
>> @@ -11,8 +11,6 @@
>>  #define SECTION_SIZE_BITS       24
>>  
>>  #define MAX_PHYSADDR_BITS       46
>> -#define MAX_PHYSMEM_BITS        46
>
> Is there now no link between those two?
>
>>  #ifdef CONFIG_MEMORY_HOTPLUG
>> diff --git a/arch/powerpc/kernel/prom.c b/arch/powerpc/kernel/prom.c
>> index 308c5e15676b..c09315b32ca7 100644
>> --- a/arch/powerpc/kernel/prom.c
>> +++ b/arch/powerpc/kernel/prom.c
>> @@ -698,9 +698,28 @@ void __init early_init_devtree(void *params)
>>  #endif
>>  		reserve_crashkernel();
>>  	early_reserve_mem();
>> -
>> -	/* Ensure that total memory size is page-aligned. */
>> -	limit = ALIGN(memory_limit ?: memblock_phys_mem_size(), PAGE_SIZE);
>> +	/*
>> +	 * if not specified limit the memory based on the pfn count that
>> +	 * we can fit in pte_t. Also ensure that total memory size is
>> +	 * page-aligned.
>
> Shouldn't you do the logic below even if memory_limit is specified? Otherwise
> someone can specify a really large memory_limit which will then overflow.
>
>> +	 */
>> +	if (!memory_limit) {
>> +		int bit_count;
>> +		phys_addr_t pte_mem_limit;
>> +
>> +		limit = memblock_phys_mem_size();
>> +		if (limit >= (1ULL << MAX_PHYSMEM_BITS))
>> +			limit = (1ULL << MAX_PHYSMEM_BITS) - 1;
>> +
>> +		BUILD_BUG_ON(sizeof(pte_basic_t) > 8);
>> +		bit_count = (sizeof(pte_basic_t) * 8) - PTE_RPN_SHIFT + PAGE_SHIFT;
>> +		pte_mem_limit = ~0ULL >> (64 - bit_count);
>
> It's fairly obvious what you're doing here, but a bit of a comment wouldn't hurt.
>
>> +		if (limit > pte_mem_limit)
>> +			limit = pte_mem_limit;
>> +	} else
>> +		limit = memory_limit;
>> +
>> +	limit = ALIGN(limit, PAGE_SIZE);
>
> cheers