From: Cyril Bur <cyrilbur@gmail.com>
To: Daniel Axtens <dja@axtens.net>
Cc: linuxppc-dev@ozlabs.org, mpe@ellerman.id.au,
benh@kernel.crashing.org,
"Matthew R. Ochs" <mrochs@linux.vnet.ibm.com>,
Manoj Kumar <kumarmn@us.ibm.com>,
mikey@neuling.org, imunsie@au.ibm.com
Subject: Re: [PATCH v3 01/11] cxl: Convert MMIO read/write macros to inline functions
Date: Wed, 12 Aug 2015 16:31:28 +1000 [thread overview]
Message-ID: <20150812163128.531d2391@camb691> (raw)
In-Reply-To: <1439340500-18610-2-git-send-email-dja@axtens.net>
On Wed, 12 Aug 2015 10:48:10 +1000
Daniel Axtens <dja@axtens.net> wrote:
> We're about to make these more complex, so make them functions
> first.
>
Reviewed-by: Cyril Bur <cyrilbur@gmail.com>
> Signed-off-by: Daniel Axtens <dja@axtens.net>
> ---
> drivers/misc/cxl/cxl.h | 51 ++++++++++++++++++++++++++++++++++----------------
> 1 file changed, 35 insertions(+), 16 deletions(-)
>
> diff --git a/drivers/misc/cxl/cxl.h b/drivers/misc/cxl/cxl.h
> index 4fd66cabde1e..6a93bfbcd826 100644
> --- a/drivers/misc/cxl/cxl.h
> +++ b/drivers/misc/cxl/cxl.h
> @@ -537,10 +537,15 @@ static inline void __iomem *_cxl_p1_addr(struct cxl *cxl, cxl_p1_reg_t reg)
> return cxl->p1_mmio + cxl_reg_off(reg);
> }
>
> -#define cxl_p1_write(cxl, reg, val) \
> - out_be64(_cxl_p1_addr(cxl, reg), val)
> -#define cxl_p1_read(cxl, reg) \
> - in_be64(_cxl_p1_addr(cxl, reg))
> +static inline void cxl_p1_write(struct cxl *cxl, cxl_p1_reg_t reg, u64 val)
> +{
> + out_be64(_cxl_p1_addr(cxl, reg), val);
> +}
> +
> +static inline u64 cxl_p1_read(struct cxl *cxl, cxl_p1_reg_t reg)
> +{
> + return in_be64(_cxl_p1_addr(cxl, reg));
> +}
>
> static inline void __iomem *_cxl_p1n_addr(struct cxl_afu *afu, cxl_p1n_reg_t reg)
> {
> @@ -548,26 +553,40 @@ static inline void __iomem *_cxl_p1n_addr(struct cxl_afu *afu, cxl_p1n_reg_t reg
> return afu->p1n_mmio + cxl_reg_off(reg);
> }
>
> -#define cxl_p1n_write(afu, reg, val) \
> - out_be64(_cxl_p1n_addr(afu, reg), val)
> -#define cxl_p1n_read(afu, reg) \
> - in_be64(_cxl_p1n_addr(afu, reg))
> +static inline void cxl_p1n_write(struct cxl_afu *afu, cxl_p1n_reg_t reg, u64 val)
> +{
> + out_be64(_cxl_p1n_addr(afu, reg), val);
> +}
> +
> +static inline u64 cxl_p1n_read(struct cxl_afu *afu, cxl_p1n_reg_t reg)
> +{
> + return in_be64(_cxl_p1n_addr(afu, reg));
> +}
>
> static inline void __iomem *_cxl_p2n_addr(struct cxl_afu *afu, cxl_p2n_reg_t reg)
> {
> return afu->p2n_mmio + cxl_reg_off(reg);
> }
>
> -#define cxl_p2n_write(afu, reg, val) \
> - out_be64(_cxl_p2n_addr(afu, reg), val)
> -#define cxl_p2n_read(afu, reg) \
> - in_be64(_cxl_p2n_addr(afu, reg))
> +static inline void cxl_p2n_write(struct cxl_afu *afu, cxl_p2n_reg_t reg, u64 val)
> +{
> + out_be64(_cxl_p2n_addr(afu, reg), val);
> +}
>
> +static inline u64 cxl_p2n_read(struct cxl_afu *afu, cxl_p2n_reg_t reg)
> +{
> + return in_be64(_cxl_p2n_addr(afu, reg));
> +}
>
> -#define cxl_afu_cr_read64(afu, cr, off) \
> - in_le64((afu)->afu_desc_mmio + (afu)->crs_offset + ((cr) * (afu)->crs_len) + (off))
> -#define cxl_afu_cr_read32(afu, cr, off) \
> - in_le32((afu)->afu_desc_mmio + (afu)->crs_offset + ((cr) * (afu)->crs_len) + (off))
> +static inline u64 cxl_afu_cr_read64(struct cxl_afu *afu, int cr, u64 off)
> +{
> + return in_le64((afu)->afu_desc_mmio + (afu)->crs_offset + ((cr) * (afu)->crs_len) + (off));
> +}
> +
> +static inline u32 cxl_afu_cr_read32(struct cxl_afu *afu, int cr, u64 off)
> +{
> + return in_le32((afu)->afu_desc_mmio + (afu)->crs_offset + ((cr) * (afu)->crs_len) + (off));
> +}
> u16 cxl_afu_cr_read16(struct cxl_afu *afu, int cr, u64 off);
> u8 cxl_afu_cr_read8(struct cxl_afu *afu, int cr, u64 off);
>
next prev parent reply other threads:[~2015-08-12 6:30 UTC|newest]
Thread overview: 17+ messages / expand[flat|nested] mbox.gz Atom feed top
2015-08-12 0:48 [PATCH v3 00/11] CXL EEH Handling Daniel Axtens
2015-08-12 0:48 ` [PATCH v3 01/11] cxl: Convert MMIO read/write macros to inline functions Daniel Axtens
2015-08-12 6:31 ` Cyril Bur [this message]
2015-08-12 0:48 ` [PATCH v3 02/11] cxl: Drop commands if the PCI channel is not in normal state Daniel Axtens
2015-08-12 6:35 ` Cyril Bur
2015-08-12 0:48 ` [PATCH v3 03/11] cxl: Allocate and release the SPA with the AFU Daniel Axtens
2015-08-12 0:48 ` [PATCH v3 04/11] cxl: Make IRQ release idempotent Daniel Axtens
2015-08-12 0:48 ` [PATCH v3 05/11] cxl: Clean up adapter MMIO unmap path Daniel Axtens
2015-08-12 0:48 ` [PATCH v3 06/11] cxl: Refactor adaptor init/teardown Daniel Axtens
2015-08-12 6:36 ` Cyril Bur
2015-08-12 0:48 ` [PATCH v3 07/11] cxl: Refactor AFU init/teardown Daniel Axtens
2015-08-12 0:48 ` [PATCH v3 08/11] cxl: Don't remove AFUs/vPHBs in cxl_reset Daniel Axtens
2015-08-12 0:48 ` [PATCH v3 09/11] cxl: Allow the kernel to trust that an image won't change on PERST Daniel Axtens
2015-08-12 6:39 ` Cyril Bur
2015-08-12 0:48 ` [PATCH v3 10/11] cxl: EEH support Daniel Axtens
2015-08-12 6:40 ` Cyril Bur
2015-08-12 0:48 ` [PATCH v3 11/11] cxl: Add CONFIG_CXL_EEH symbol Daniel Axtens
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