From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from newverein.lst.de (verein.lst.de [213.95.11.211]) (using TLSv1.2 with cipher AECDH-AES256-SHA (256/256 bits)) (No client certificate requested) by lists.ozlabs.org (Postfix) with ESMTPS id 399EF1A1D58 for ; Fri, 14 Aug 2015 00:40:53 +1000 (AEST) Date: Thu, 13 Aug 2015 16:31:50 +0200 From: Christoph Hellwig To: Linus Torvalds Cc: Jens Axboe , Dan Williams , Vineet Gupta , =?iso-8859-1?Q?H=E5vard?= Skinnemoen , Hans-Christian Egtvedt , Miao Steven , David Howells , Michal Simek , the arch/x86 maintainers , David Woodhouse , Alex Williamson , grundler@parisc-linux.org, Linux Kernel Mailing List , "linux-arch@vger.kernel.org" , linux-alpha@vger.kernel.org, "linux-ia64@vger.kernel.org" , linux-metag@vger.kernel.org, linux-mips , Parisc List , ppc-dev , linux-s390 , sparclinux@vger.kernel.org, linux-xtensa@linux-xtensa.org, "linux-nvdimm@lists.01.org" , Linux Media Mailing List Subject: Re: [PATCH 29/31] parisc: handle page-less SG entries Message-ID: <20150813143150.GA17183@lst.de> References: <1439363150-8661-1-git-send-email-hch@lst.de> <1439363150-8661-30-git-send-email-hch@lst.de> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii In-Reply-To: List-Id: Linux on PowerPC Developers Mail List List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , On Wed, Aug 12, 2015 at 09:01:02AM -0700, Linus Torvalds wrote: > I'm assuming that anybody who wants to use the page-less > scatter-gather lists always does so on memory that isn't actually > virtually mapped at all, or only does so on sane architectures that > are cache coherent at a physical level, but I'd like that assumption > *documented* somewhere. It's temporarily mapped by kmap-like helpers. That code isn't in this series. The most recent version of it is here: https://git.kernel.org/cgit/linux/kernel/git/djbw/nvdimm.git/commit/?h=pfn&id=de8237c99fdb4352be2193f3a7610e902b9bb2f0 note that it's not doing the cache flushing it would have to do yet, but it's also only enabled for x86 at the moment.