From: Michael Ellerman <mpe@ellerman.id.au>
To: Samuel Mendoza-Jonas <sam.mj@au1.ibm.com>, linuxppc-dev@ozlabs.org
Cc: Samuel Mendoza-Jonas <sam.mj@au1.ibm.com>
Subject: Re: [V4,2/2] powerpc/kexec: Reset HILE before kexec_sequence
Date: Fri, 21 Aug 2015 17:43:35 +1000 (AEST) [thread overview]
Message-ID: <20150821074335.4B34E1402AC@ozlabs.org> (raw)
In-Reply-To: <1437544251-19016-3-git-send-email-sam.mj@au1.ibm.com>
On Wed, 2015-22-07 at 05:50:51 UTC, Samuel Mendoza-Jonas wrote:
> On powernv secondary cpus are returned to OPAL, and will then enter
> the target kernel in big-endian. However if it is set the HILE bit
> will persist, causing the first exception in the target kernel to be
> delivered in litte-endian regardless of the current endianess.
>
> If running on top of OPAL make sure the HILE bit is reset once we've
> finished waiting for all of the secondaries to be returned to OPAL.
>
> Signed-off-by: Samuel Mendoza-Jonas <sam.mj@au1.ibm.com>
Applied to powerpc next, thanks.
https://git.kernel.org/powerpc/c/e72bb8a5a884d0222311
cheers
prev parent reply other threads:[~2015-08-21 7:43 UTC|newest]
Thread overview: 5+ messages / expand[flat|nested] mbox.gz Atom feed top
2015-07-22 5:50 [PATCH V4 0/2] powerpc/kexec: Reset endianess before kexec Samuel Mendoza-Jonas
2015-07-22 5:50 ` [PATCH V4 1/2] powerpc/kexec: Reset secondary cpu " Samuel Mendoza-Jonas
2015-08-21 7:43 ` [V4, " Michael Ellerman
2015-07-22 5:50 ` [PATCH V4 2/2] powerpc/kexec: Reset HILE before kexec_sequence Samuel Mendoza-Jonas
2015-08-21 7:43 ` Michael Ellerman [this message]
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