From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from gate.crashing.org (gate.crashing.org [63.228.1.57]) (using TLSv1 with cipher DHE-RSA-AES256-SHA (256/256 bits)) (No client certificate requested) by lists.ozlabs.org (Postfix) with ESMTPS id 3581F1A0017 for ; Sat, 3 Oct 2015 08:01:00 +1000 (AEST) Date: Fri, 2 Oct 2015 17:00:51 -0500 From: Segher Boessenkool To: Denis Kirjanov Cc: Peter Bergner , "linuxppc-dev@lists.ozlabs.org" , Laura Abbott , Paul Mackerras , Linux Kernel Mailing List Subject: Re: Missing operand for tlbie instruction on Power7 Message-ID: <20151002220051.GA26712@gate.crashing.org> References: <560EA623.1040300@redhat.com> <1443816930.13186.214.camel@otta> Mime-Version: 1.0 Content-Type: text/plain; charset=us-ascii In-Reply-To: List-Id: Linux on PowerPC Developers Mail List List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , On Sat, Oct 03, 2015 at 12:37:35AM +0300, Denis Kirjanov wrote: > >> -0: tlbie r4; \ > >> +0: tlbie r4, 0; \ > > > > This isn't correct. With POWER7 and later (which this compile > > is, since it's on LE), the tlbie instruction takes two register > > operands: > > > > tlbie RB, RS > > > > The tlbie instruction on pre POWER7 cpus had one required register > > operand (RB) and an optional second L operand, where if you omitted > > it, it was the same as using "0": > > > > tlbie RB, L > > > > This is a POWER7 and later build, so your change which adds the "0" > > above is really adding r0 for RS. The new tlbie instruction doesn't > > treat r0 specially, so you'll be using whatever random bits which > > happen to be in r0 which I don't think that is what you want. > > Ok, than we can just zero out r5 for example and use it in tlbie as RS, > right? That won't assemble _unless_ your assembler is in POWER7 mode. It also won't do the right thing at run time on older machines. Where is this tlbia macro used at all, for 64-bit machines? Segher