From: "Paul E. McKenney" <paulmck@linux.vnet.ibm.com>
To: Boqun Feng <boqun.feng@gmail.com>
Cc: Peter Zijlstra <peterz@infradead.org>,
linux-kernel@vger.kernel.org, linuxppc-dev@lists.ozlabs.org,
Ingo Molnar <mingo@kernel.org>,
Benjamin Herrenschmidt <benh@kernel.crashing.org>,
Paul Mackerras <paulus@samba.org>,
Michael Ellerman <mpe@ellerman.id.au>,
Thomas Gleixner <tglx@linutronix.de>,
Will Deacon <will.deacon@arm.com>,
Waiman Long <waiman.long@hp.com>
Subject: Re: [RFC v2 4/7] powerpc: atomic: Implement xchg_* and atomic{,64}_xchg_* variants
Date: Mon, 12 Oct 2015 16:24:26 -0700 [thread overview]
Message-ID: <20151012232426.GJ3910@linux.vnet.ibm.com> (raw)
In-Reply-To: <20151012011749.GD27351@fixme-laptop.cn.ibm.com>
On Mon, Oct 12, 2015 at 09:17:50AM +0800, Boqun Feng wrote:
> Hi Paul,
>
> On Thu, Oct 01, 2015 at 11:03:01AM -0700, Paul E. McKenney wrote:
> > On Thu, Oct 01, 2015 at 07:13:04PM +0200, Peter Zijlstra wrote:
> > > On Thu, Oct 01, 2015 at 08:09:09AM -0700, Paul E. McKenney wrote:
> > > > On Thu, Oct 01, 2015 at 02:24:40PM +0200, Peter Zijlstra wrote:
> > >
> > > > > I must say I'm somewhat surprised by this level of relaxation, I had
> > > > > expected to only loose SMP barriers, not the program order ones.
> > > > >
> > > > > Is there a good argument for this?
> > > >
> > > > Yes, when we say "relaxed", we really mean relaxed. ;-)
> > > >
> > > > Both the CPU and the compiler are allowed to reorder around relaxed
> > > > operations.
> > >
> > > Is this documented somewhere, because I completely missed this part.
> >
> > Well, yes, these need to be added to the documentation. I am assuming
>
> Maybe it's good time for us to call it out which operation should be
> a compiler barrier or a CPU barrier?
>
> I had something in my mind while I was working on this series, not
> really sure whether it's correct, but probably a start point:
>
> All global and local atomic operations are at least atomic(no one can
> observe the middle state) and volatile(compilers can't optimize out the
> memory access). Based on this, there are four strictness levels, one
> can rely on them:
>
> RELAXED: neither a compiler barrier or a CPU barrier
> LOCAL: a compiler barrier
> PARTIAL: both a compiler barrier and a CPU barrier but not transitive
> FULL: both compiler barrier and a CPU barrier, and transitive.
As Will noted, we have two types of transitive. The first type is that
of release-acquire chains, where the transitivity is only observable
within the chain. The second type is that of smp_mb(), where the
transitivity is observable globally.
Thanx, Paul
> RELAXED includes all _relaxed variants and non-return atomics, LOCAL
> includes all local atomics(local_* and {cmp}xchg_local), PARTIAL
> includes _acquire and _release operations and FULL includes all fully
> ordered global atomic operations.
>
> Thoughts?
>
> Regards,
> Boqun
>
> > that Will is looking to have the same effect as C11 memory_order_relaxed,
> > which is relaxed in this sense. If he has something else in mind,
> > he needs to tell us what it is and why. ;-)
> >
> > Thanx, Paul
> >
next prev parent reply other threads:[~2015-10-12 23:24 UTC|newest]
Thread overview: 43+ messages / expand[flat|nested] mbox.gz Atom feed top
2015-09-16 15:49 [RFC v2 0/7] atomics: powerpc: Implement relaxed/acquire/release variants of some atomics Boqun Feng
2015-09-16 15:49 ` [RFC v2 1/7] atomics: Add test for atomic operations with _relaxed variants Boqun Feng
2015-10-12 9:30 ` Will Deacon
2015-10-12 9:38 ` Boqun Feng
2015-09-16 15:49 ` [RFC v2 2/7] atomics: Allow architectures to define their own __atomic_op_* helpers Boqun Feng
2015-09-16 15:49 ` [RFC v2 3/7] powerpc: atomic: Implement atomic{, 64}_{add, sub}_return_* variants Boqun Feng
2015-09-18 16:59 ` [RFC v2 3/7] powerpc: atomic: Implement atomic{,64}_{add,sub}_return_* variants Will Deacon
2015-09-19 15:33 ` Boqun Feng
2015-09-20 8:23 ` Boqun Feng
2015-09-21 22:24 ` Will Deacon
2015-09-21 23:26 ` Boqun Feng
2015-09-21 23:37 ` Boqun Feng
2015-09-22 15:25 ` Paul E. McKenney
2015-09-23 0:07 ` Boqun Feng
2015-09-25 21:29 ` Paul E. McKenney
2015-09-26 2:18 ` Boqun Feng
2015-09-16 15:49 ` [RFC v2 4/7] powerpc: atomic: Implement xchg_* and atomic{, 64}_xchg_* variants Boqun Feng
2015-10-01 12:24 ` [RFC v2 4/7] powerpc: atomic: Implement xchg_* and atomic{,64}_xchg_* variants Peter Zijlstra
2015-10-01 15:09 ` Paul E. McKenney
2015-10-01 17:13 ` Peter Zijlstra
2015-10-01 18:03 ` Paul E. McKenney
2015-10-01 18:23 ` Peter Zijlstra
2015-10-01 19:41 ` Paul E. McKenney
2015-10-05 14:44 ` Will Deacon
2015-10-05 16:57 ` Paul E. McKenney
2015-10-12 1:17 ` Boqun Feng
2015-10-12 9:28 ` Will Deacon
2015-10-12 23:24 ` Paul E. McKenney [this message]
2015-09-16 15:49 ` [RFC v2 5/7] powerpc: atomic: Implement cmpxchg{, 64}_* and atomic{, 64}_cmpxchg_* variants Boqun Feng
2015-10-01 12:27 ` [RFC v2 5/7] powerpc: atomic: Implement cmpxchg{,64}_* and atomic{,64}_cmpxchg_* variants Peter Zijlstra
2015-10-01 12:36 ` Peter Zijlstra
2015-10-01 15:12 ` Paul E. McKenney
2015-10-01 17:11 ` Peter Zijlstra
2015-10-01 15:13 ` Paul E. McKenney
2015-10-10 1:58 ` Boqun Feng
2015-10-11 10:25 ` Boqun Feng
2015-10-12 6:46 ` Peter Zijlstra
2015-10-12 7:03 ` Boqun Feng
2015-09-16 15:49 ` [RFC v2 6/7] powerpc: atomic: Make atomic{, 64}_xchg and xchg a full barrier Boqun Feng
2015-10-01 12:28 ` [RFC v2 6/7] powerpc: atomic: Make atomic{,64}_xchg " Peter Zijlstra
2015-10-01 23:19 ` Boqun Feng
2015-10-02 5:25 ` Peter Zijlstra
2015-09-16 15:49 ` [RFC v2 7/7] powerpc: atomic: Make atomic{, 64}_cmpxchg and cmpxchg " Boqun Feng
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