Re: [PATCH v9 26/26] powerpc/powernv: Exclude root bus in pnv_pci_reset_secondary_bus()

[Gavin Shan <gwshan@linux.vnet.ibm.com>]

On Tue, May 03, 2016 at 03:41:45PM +1000, Gavin Shan wrote:
>The function pnv_pci_reset_secondary_bus() is called like below.
>It's impossible for call the function on root bus. So it's safe
>to remove the root bus case in the function. No functional changes
>introduced.
>
>   pci_parent_bus_reset() / pci_bus_reset() / pci_try_reset_bus()
>   pci_reset_bridge_secondary_bus()
>   pcibios_reset_secondary_bus()
>   pnv_pci_reset_secondary_bus()
>
>Signed-off-by: Gavin Shan <gwshan@linux.vnet.ibm.com>
>Reviewed-by: Daniel Axtens <dja@axtens.net>
>Reviewed-by: Alexey Kardashevskiy <aik@ozlabs.ru>
>---
> arch/powerpc/platforms/powernv/eeh-powernv.c | 12 ++----------
> 1 file changed, 2 insertions(+), 10 deletions(-)
>
>diff --git a/arch/powerpc/platforms/powernv/eeh-powernv.c b/arch/powerpc/platforms/powernv/eeh-powernv.c
>index 9226df1..593b8dc 100644
>--- a/arch/powerpc/platforms/powernv/eeh-powernv.c
>+++ b/arch/powerpc/platforms/powernv/eeh-powernv.c
>@@ -868,16 +868,8 @@ static int pnv_eeh_bridge_reset(struct pci_dev *dev, int option)
>
> void pnv_pci_reset_secondary_bus(struct pci_dev *dev)
> {
>-	struct pci_controller *hose;
>-
>-	if (pci_is_root_bus(dev->bus)) {
>-		hose = pci_bus_to_host(dev->bus);
>-		pnv_eeh_root_reset(hose, EEH_RESET_HOT);
>-		pnv_eeh_root_reset(hose, EEH_RESET_DEACTIVATE);
>-	} else {
>-		pnv_eeh_bridge_reset(dev, EEH_RESET_HOT);
>-		pnv_eeh_bridge_reset(dev, EEH_RESET_DEACTIVATE);
>-	}
>+	pnv_eeh_bridge_reset(dev, EEH_RESET_HOT);
>+	pnv_eeh_bridge_reset(dev, EEH_RESET_DEACTIVATE);
> }

Michael, please revert this one as it is already in linux-ppc-next
branch. Sorry for the overhead.

Obviously, I missed the truth that it affects the PCI passthrou path as
reported by Alexey: When passing GPU (0003:01:00.0) which seats behind
the root port, the reset request is routed to skiboot in original code.
In skiboot, the link bouncing events are masked during the reset. So we
don't see EEH (freeze all) error even link bouncing happens. With the
changes included, the reset is done by kernel and the link bouncing
events aren't masked by altering content of PHB3 (or P7IOC) specific
hardware registers which are invisible to kernel (skiboot hides the
hardware specific). It means the link bouncing is seen by the root port
and it causes a EEH (freeze all) error. The PCI passthrough on GPU device
cannot work.

Thanks,
Gavin

>
> static void pnv_eeh_wait_for_pending(struct pci_dn *pdn, const char *type,
>-- 
>2.1.0
>