From mboxrd@z Thu Jan  1 00:00:00 1970
Return-Path: <oss@buserror.net>
Received: from host.buserror.net (host.buserror.net [209.198.135.123])
 (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits))
 (No client certificate requested)
 by lists.ozlabs.org (Postfix) with ESMTPS id 3r7xM04tFvzDq5f
 for <linuxppc-dev@lists.ozlabs.org>; Tue, 17 May 2016 09:22:20 +1000 (AEST)
Date: Mon, 16 May 2016 18:22:10 -0500
From: Scott Wood <oss@buserror.net>
To: Zhao Qiang <qiang.zhao@nxp.com>
Cc: robh+dt@kernel.org, devicetree@vger.kernel.org,
 linux-kernel@vger.kernel.org, xiaobo.xie@nxp.com,
 leoyang.li@nxp.com, linuxppc-dev@lists.ozlabs.org
Message-ID: <20160516232210.GA21087@home.buserror.net>
References: <1457486494-11377-1-git-send-email-qiang.zhao@nxp.com>
MIME-Version: 1.0
Content-Type: text/plain; charset=us-ascii
In-Reply-To: <1457486494-11377-1-git-send-email-qiang.zhao@nxp.com>
Subject: Re: [v5,1/7] QE: Add IC, SI and SIRAM document to device tree
 bindings.
List-Id: Linux on PowerPC Developers Mail List <linuxppc-dev.lists.ozlabs.org>
List-Unsubscribe: <https://lists.ozlabs.org/options/linuxppc-dev>,
 <mailto:linuxppc-dev-request@lists.ozlabs.org?subject=unsubscribe>
List-Archive: <http://lists.ozlabs.org/pipermail/linuxppc-dev/>
List-Post: <mailto:linuxppc-dev@lists.ozlabs.org>
List-Help: <mailto:linuxppc-dev-request@lists.ozlabs.org?subject=help>
List-Subscribe: <https://lists.ozlabs.org/listinfo/linuxppc-dev>,
 <mailto:linuxppc-dev-request@lists.ozlabs.org?subject=subscribe>

On Wed, Mar 09, 2016 at 09:21:28AM +0800, Zhao Qiang wrote:
> Add IC, SI and SIRAM document of QE to
> Documentation/devicetree/bindings/powerpc/fsl/cpm_qe/qe.txt
> 
> Signed-off-by: Zhao Qiang <qiang.zhao@nxp.com>
> Acked-by: Rob Herring <robh@kernel.org>
> ---
> changes for v2
> 	- Add interrupt-controller in Required properties
> 	- delete address-cells and size-cells for qe-si and qe-siram
> Changes for v3
> 	- Add SoC specific caompatible strings to qe-si and qe-siram
> Changes for v4
> 	- NA 
> Changes for v5
> 	- NA 
> 
>  .../devicetree/bindings/powerpc/fsl/cpm_qe/qe.txt  | 50 ++++++++++++++++++++++
>  1 file changed, 50 insertions(+)
> 
> diff --git a/Documentation/devicetree/bindings/powerpc/fsl/cpm_qe/qe.txt b/Documentation/devicetree/bindings/powerpc/fsl/cpm_qe/qe.txt
> index 4f89302..7ab21cb 100644
> --- a/Documentation/devicetree/bindings/powerpc/fsl/cpm_qe/qe.txt
> +++ b/Documentation/devicetree/bindings/powerpc/fsl/cpm_qe/qe.txt
> @@ -69,6 +69,56 @@ Example:
>  	};
>       };
>  
> +* Interrupt Controller (IC)
> +
> +Required properties:
> +- compatible : should be "fsl,qe-ic".
> +- reg : Address range of IC register set.
> +- interrupts : interrupts generated by the device.
> +- interrupt-controller : this device is a interrupt controller.
> +
> +Example:
> +
> +	qeic: interrupt-controller@80 {
> +		interrupt-controller;
> +		compatible = "fsl,qe-ic";
> +		#address-cells = <0>;
> +		#interrupt-cells = <1>;
> +		reg = <0x80 0x80>;
> +		interrupts = <95 2 0 0  94 2 0 0>; //high:79 low:78
> +	};

Why is the information about which interrupt is "high" and which is
"low" in a comment in the example, rather than in the definition of the
interrupts property?

> +* Serial Interface Block (SI)
> +
> +The SI manages the routing of eight TDM lines to the QE block serial drivers
> +, the MCC and the UCCs, for receive and transmit.
> +
> +Required properties:
> +- compatible : should be "fsl,t1040-qe-si".
> +- reg : Address range of SI register set.

Is t1040 the only chip that has or will ever have this?

-Scott