From: David Miller <davem@davemloft.net>
To: qiang.zhao@nxp.com
Cc: oss@buserror.net, linuxppc-dev@lists.ozlabs.org,
linux-kernel@vger.kernel.org, netdev@vger.kernel.org,
xiaobo.xie@nxp.com
Subject: Re: [PATCH v2 2/5] fsl/qe: setup clock source for TDM mode
Date: Thu, 02 Jun 2016 12:24:51 -0700 (PDT) [thread overview]
Message-ID: <20160602.122451.160749876120675817.davem@davemloft.net> (raw)
In-Reply-To: <1464831901-15913-2-git-send-email-qiang.zhao@nxp.com>
From: Zhao Qiang <qiang.zhao@nxp.com>
Date: Thu, 2 Jun 2016 09:44:58 +0800
> +static int ucc_get_tdm_sync_source(u32 tdm_num, enum qe_clock clock,
> + enum comm_dir mode)
> +{
> + int source = -EINVAL;
> +
> + if (mode == COMM_DIR_RX && clock == QE_RSYNC_PIN) {
> + source = 0;
> + return source;
> + }
> + if (mode == COMM_DIR_TX && clock == QE_TSYNC_PIN) {
> + source = 0;
> + return source;
> + }
> +
> + switch (tdm_num) {
> + case 0:
> + case 1:
> + switch (clock) {
> + case QE_BRG9:
> + source = 1;
> + break;
> + case QE_BRG10:
> + source = 2;
> + break;
These switch case bodies are over indented. Same goes for the rest of
this function.
next prev parent reply other threads:[~2016-06-02 19:24 UTC|newest]
Thread overview: 7+ messages / expand[flat|nested] mbox.gz Atom feed top
2016-06-02 1:44 [PATCH v2 1/5] fsl/qe: add rx_sync and tx_sync for TDM mode Zhao Qiang
2016-06-02 1:44 ` [PATCH v2 2/5] fsl/qe: setup clock source " Zhao Qiang
2016-06-02 19:24 ` David Miller [this message]
2016-06-02 1:44 ` [PATCH v2 3/5] fsl/qe: Make regs resouce_size_t Zhao Qiang
2016-06-02 1:45 ` [PATCH v2 4/5] fsl/qe: Add QE TDM lib Zhao Qiang
2016-06-02 1:45 ` [Patch v2 5/5] drivers/net: support hdlc function for QE-UCC Zhao Qiang
2016-06-02 7:37 ` Joakim Tjernlund
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