* [PATCH for-4.8 01/12] Fix .long's in mm/tlb-radix.c to more meaningful
2016-07-13 9:35 [PATCH for-4.8_set1 00/12] Radix fixes for 4.8 Aneesh Kumar K.V
@ 2016-07-13 9:35 ` Aneesh Kumar K.V
2016-07-17 10:28 ` [for-4.8,01/12] " Michael Ellerman
2016-07-13 9:35 ` [PATCH for-4.8 02/12] powerpc/mm/radix: Update LPCR HR bit as per ISA Aneesh Kumar K.V
` (10 subsequent siblings)
11 siblings, 1 reply; 24+ messages in thread
From: Aneesh Kumar K.V @ 2016-07-13 9:35 UTC (permalink / raw)
To: benh, paulus, mpe; +Cc: linuxppc-dev, Balbir Singh, Aneesh Kumar K . V
From: Balbir Singh <bsingharora@gmail.com>
The .longs with the shifts are harder to read, use more
meaningful names for the opcodes. PPC_TLBIE_5 is introduced
for the 5 opcode variation of the instruction due to an existing
op-code for the 2 opcode variant
Signed-off-by: Balbir Singh <bsingharora@gmail.com>
Signed-off-by: Aneesh Kumar K.V <aneesh.kumar@linux.vnet.ibm.com>
---
arch/powerpc/include/asm/ppc-opcode.h | 14 ++++++++++++++
arch/powerpc/mm/tlb-radix.c | 13 +++++--------
2 files changed, 19 insertions(+), 8 deletions(-)
diff --git a/arch/powerpc/include/asm/ppc-opcode.h b/arch/powerpc/include/asm/ppc-opcode.h
index 9de9df14a8d9..1c9b1d4386ba 100644
--- a/arch/powerpc/include/asm/ppc-opcode.h
+++ b/arch/powerpc/include/asm/ppc-opcode.h
@@ -190,6 +190,7 @@
#define PPC_INST_STSWX 0x7c00052a
#define PPC_INST_STXVD2X 0x7c000798
#define PPC_INST_TLBIE 0x7c000264
+#define PPC_INST_TLBIEL 0x7c000224
#define PPC_INST_TLBILX 0x7c000024
#define PPC_INST_WAIT 0x7c00007c
#define PPC_INST_TLBIVAX 0x7c000624
@@ -279,6 +280,9 @@
#define ___PPC_RB(b) (((b) & 0x1f) << 11)
#define ___PPC_RS(s) (((s) & 0x1f) << 21)
#define ___PPC_RT(t) ___PPC_RS(t)
+#define ___PPC_R(r) (((r) & 0x1) << 16)
+#define ___PPC_PRS(prs) (((prs) & 0x1) << 17)
+#define ___PPC_RIC(ric) (((ric) & 0x3) << 18)
#define __PPC_RA(a) ___PPC_RA(__REG_##a)
#define __PPC_RA0(a) ___PPC_RA(__REGA0_##a)
#define __PPC_RB(b) ___PPC_RB(__REG_##b)
@@ -345,6 +349,16 @@
__PPC_WC(w))
#define PPC_TLBIE(lp,a) stringify_in_c(.long PPC_INST_TLBIE | \
___PPC_RB(a) | ___PPC_RS(lp))
+#define PPC_TLBIE_5(rb,rs,ric,prs,r) \
+ stringify_in_c(.long PPC_INST_TLBIE | \
+ ___PPC_RB(rb) | ___PPC_RS(rs) | \
+ ___PPC_RIC(ric) | ___PPC_PRS(prs) | \
+ ___PPC_R(r))
+#define PPC_TLBIEL(rb,rs,ric,prs,r) \
+ stringify_in_c(.long PPC_INST_TLBIEL | \
+ ___PPC_RB(rb) | ___PPC_RS(rs) | \
+ ___PPC_RIC(ric) | ___PPC_PRS(prs) | \
+ ___PPC_R(r))
#define PPC_TLBSRX_DOT(a,b) stringify_in_c(.long PPC_INST_TLBSRX_DOT | \
__PPC_RA0(a) | __PPC_RB(b))
#define PPC_TLBIVAX(a,b) stringify_in_c(.long PPC_INST_TLBIVAX | \
diff --git a/arch/powerpc/mm/tlb-radix.c b/arch/powerpc/mm/tlb-radix.c
index ab2f60e812e2..35690c41f85d 100644
--- a/arch/powerpc/mm/tlb-radix.c
+++ b/arch/powerpc/mm/tlb-radix.c
@@ -12,6 +12,7 @@
#include <linux/mm.h>
#include <linux/hugetlb.h>
#include <linux/memblock.h>
+#include <asm/ppc-opcode.h>
#include <asm/tlb.h>
#include <asm/tlbflush.h>
@@ -34,8 +35,7 @@ static inline void __tlbiel_pid(unsigned long pid, int set,
r = 1; /* raidx format */
asm volatile("ptesync": : :"memory");
- asm volatile(".long 0x7c000224 | (%0 << 11) | (%1 << 16) |"
- "(%2 << 17) | (%3 << 18) | (%4 << 21)"
+ asm volatile(PPC_TLBIEL(%0, %4, %3, %2, %1)
: : "r"(rb), "i"(r), "i"(prs), "i"(ric), "r"(rs) : "memory");
asm volatile("ptesync": : :"memory");
}
@@ -63,8 +63,7 @@ static inline void _tlbie_pid(unsigned long pid, unsigned long ric)
r = 1; /* raidx format */
asm volatile("ptesync": : :"memory");
- asm volatile(".long 0x7c000264 | (%0 << 11) | (%1 << 16) |"
- "(%2 << 17) | (%3 << 18) | (%4 << 21)"
+ asm volatile(PPC_TLBIE_5(%0, %4, %3, %2, %1)
: : "r"(rb), "i"(r), "i"(prs), "i"(ric), "r"(rs) : "memory");
asm volatile("eieio; tlbsync; ptesync": : :"memory");
}
@@ -81,8 +80,7 @@ static inline void _tlbiel_va(unsigned long va, unsigned long pid,
r = 1; /* raidx format */
asm volatile("ptesync": : :"memory");
- asm volatile(".long 0x7c000224 | (%0 << 11) | (%1 << 16) |"
- "(%2 << 17) | (%3 << 18) | (%4 << 21)"
+ asm volatile(PPC_TLBIEL(%0, %4, %3, %2, %1)
: : "r"(rb), "i"(r), "i"(prs), "i"(ric), "r"(rs) : "memory");
asm volatile("ptesync": : :"memory");
}
@@ -99,8 +97,7 @@ static inline void _tlbie_va(unsigned long va, unsigned long pid,
r = 1; /* raidx format */
asm volatile("ptesync": : :"memory");
- asm volatile(".long 0x7c000264 | (%0 << 11) | (%1 << 16) |"
- "(%2 << 17) | (%3 << 18) | (%4 << 21)"
+ asm volatile(PPC_TLBIE_5(%0, %4, %3, %2, %1)
: : "r"(rb), "i"(r), "i"(prs), "i"(ric), "r"(rs) : "memory");
asm volatile("eieio; tlbsync; ptesync": : :"memory");
}
--
2.7.4
^ permalink raw reply related [flat|nested] 24+ messages in thread* [PATCH for-4.8 02/12] powerpc/mm/radix: Update LPCR HR bit as per ISA
2016-07-13 9:35 [PATCH for-4.8_set1 00/12] Radix fixes for 4.8 Aneesh Kumar K.V
2016-07-13 9:35 ` [PATCH for-4.8 01/12] Fix .long's in mm/tlb-radix.c to more meaningful Aneesh Kumar K.V
@ 2016-07-13 9:35 ` Aneesh Kumar K.V
2016-07-14 3:30 ` Balbir Singh
2016-07-13 9:35 ` [PATCH for-4.8 03/12] powerpc/mm: use _raw variant of page table accessors Aneesh Kumar K.V
` (9 subsequent siblings)
11 siblings, 1 reply; 24+ messages in thread
From: Aneesh Kumar K.V @ 2016-07-13 9:35 UTC (permalink / raw)
To: benh, paulus, mpe; +Cc: linuxppc-dev, Aneesh Kumar K.V
PowerISA 3.0 requires the MMU mode (radix vs. hash) of the hypervisor
to be mirrored in the LPCR register, in addition to the partition table.
This is done to avoid fetching from the table when deciding, among other
things, how to perform transitions to HV mode on some interrupts.
So let's set it up appropriately
Signed-off-by: Aneesh Kumar K.V <aneesh.kumar@linux.vnet.ibm.com>
---
arch/powerpc/include/asm/reg.h | 1 +
arch/powerpc/mm/pgtable-radix.c | 4 ++--
2 files changed, 3 insertions(+), 2 deletions(-)
diff --git a/arch/powerpc/include/asm/reg.h b/arch/powerpc/include/asm/reg.h
index 320136f5fe28..a5ba263e0353 100644
--- a/arch/powerpc/include/asm/reg.h
+++ b/arch/powerpc/include/asm/reg.h
@@ -354,6 +354,7 @@
#define LPCR_RMI 0x00000002 /* real mode is cache inhibit */
#define LPCR_HDICE 0x00000001 /* Hyp Decr enable (HV,PR,EE) */
#define LPCR_UPRT 0x00400000 /* Use Process Table (ISA 3) */
+#define LPCR_HR 0x00100000
#ifndef SPRN_LPID
#define SPRN_LPID 0x13F /* Logical Partition Identifier */
#endif
diff --git a/arch/powerpc/mm/pgtable-radix.c b/arch/powerpc/mm/pgtable-radix.c
index e58707deef5c..f8a3bec315f7 100644
--- a/arch/powerpc/mm/pgtable-radix.c
+++ b/arch/powerpc/mm/pgtable-radix.c
@@ -337,7 +337,7 @@ void __init radix__early_init_mmu(void)
radix_init_page_sizes();
if (!firmware_has_feature(FW_FEATURE_LPAR)) {
lpcr = mfspr(SPRN_LPCR);
- mtspr(SPRN_LPCR, lpcr | LPCR_UPRT);
+ mtspr(SPRN_LPCR, lpcr | LPCR_UPRT | LPCR_HR);
radix_init_partition_table();
}
@@ -352,7 +352,7 @@ void radix__early_init_mmu_secondary(void)
*/
if (!firmware_has_feature(FW_FEATURE_LPAR)) {
lpcr = mfspr(SPRN_LPCR);
- mtspr(SPRN_LPCR, lpcr | LPCR_UPRT);
+ mtspr(SPRN_LPCR, lpcr | LPCR_UPRT | LPCR_HR);
mtspr(SPRN_PTCR,
__pa(partition_tb) | (PATB_SIZE_SHIFT - 12));
--
2.7.4
^ permalink raw reply related [flat|nested] 24+ messages in thread* Re: [PATCH for-4.8 02/12] powerpc/mm/radix: Update LPCR HR bit as per ISA
2016-07-13 9:35 ` [PATCH for-4.8 02/12] powerpc/mm/radix: Update LPCR HR bit as per ISA Aneesh Kumar K.V
@ 2016-07-14 3:30 ` Balbir Singh
0 siblings, 0 replies; 24+ messages in thread
From: Balbir Singh @ 2016-07-14 3:30 UTC (permalink / raw)
To: Aneesh Kumar K.V; +Cc: benh, paulus, mpe, linuxppc-dev
On Wed, Jul 13, 2016 at 03:05:21PM +0530, Aneesh Kumar K.V wrote:
> PowerISA 3.0 requires the MMU mode (radix vs. hash) of the hypervisor
> to be mirrored in the LPCR register, in addition to the partition table.
> This is done to avoid fetching from the table when deciding, among other
> things, how to perform transitions to HV mode on some interrupts.
> So let's set it up appropriately
>
> Signed-off-by: Aneesh Kumar K.V <aneesh.kumar@linux.vnet.ibm.com>
> ---
Acked-by: Balbir Singh <bsingharora@gmail.com>
^ permalink raw reply [flat|nested] 24+ messages in thread
* [PATCH for-4.8 03/12] powerpc/mm: use _raw variant of page table accessors
2016-07-13 9:35 [PATCH for-4.8_set1 00/12] Radix fixes for 4.8 Aneesh Kumar K.V
2016-07-13 9:35 ` [PATCH for-4.8 01/12] Fix .long's in mm/tlb-radix.c to more meaningful Aneesh Kumar K.V
2016-07-13 9:35 ` [PATCH for-4.8 02/12] powerpc/mm/radix: Update LPCR HR bit as per ISA Aneesh Kumar K.V
@ 2016-07-13 9:35 ` Aneesh Kumar K.V
2016-07-14 3:42 ` Balbir Singh
2016-07-15 11:42 ` David Laight
2016-07-13 9:35 ` [PATCH for-4.8 04/12] powerpc/mm: Compile out radix related functions if RADIX_MMU is disabled Aneesh Kumar K.V
` (8 subsequent siblings)
11 siblings, 2 replies; 24+ messages in thread
From: Aneesh Kumar K.V @ 2016-07-13 9:35 UTC (permalink / raw)
To: benh, paulus, mpe; +Cc: linuxppc-dev, Aneesh Kumar K.V
This switch few of the page table accessor to use the __raw variant
and does the cpu to big endian conversion of constants. This helps in
generating better code.
For ex: a pgd_none(pgd) check with and without fix is listed below
Without fix:
------------
2240: 20 00 61 eb ld r27,32(r1)
/* PGD level */
typedef struct { __be64 pgd; } pgd_t;
static inline unsigned long pgd_val(pgd_t x)
{
return be64_to_cpu(x.pgd);
2244: 22 00 66 78 rldicl r6,r3,32,32
2248: 3e 40 7d 54 rotlwi r29,r3,8
224c: 0e c0 7d 50 rlwimi r29,r3,24,0,7
2250: 3e 40 c5 54 rotlwi r5,r6,8
2254: 2e c4 7d 50 rlwimi r29,r3,24,16,23
2258: 0e c0 c5 50 rlwimi r5,r6,24,0,7
225c: 2e c4 c5 50 rlwimi r5,r6,24,16,23
2260: c6 07 bd 7b rldicr r29,r29,32,31
2264: 78 2b bd 7f or r29,r29,r5
if (pgd_none(pgd))
2268: 00 00 bd 2f cmpdi cr7,r29,0
226c: 54 03 9e 41 beq cr7,25c0 <__get_user_pages_fast+0x500>
With fix:
---------
2370: 20 00 61 eb ld r27,32(r1)
if (pgd_none(pgd))
2374: 00 00 bd 2f cmpdi cr7,r29,0
2378: a8 03 9e 41 beq cr7,2720 <__get_user_pages_fast+0x530>
break;
Signed-off-by: Aneesh Kumar K.V <aneesh.kumar@linux.vnet.ibm.com>
---
arch/powerpc/include/asm/book3s/64/pgtable-4k.h | 6 +-
arch/powerpc/include/asm/book3s/64/pgtable-64k.h | 6 +-
arch/powerpc/include/asm/book3s/64/pgtable.h | 99 +++++++++++++++++-------
arch/powerpc/include/asm/pgtable-be-types.h | 15 ++++
4 files changed, 91 insertions(+), 35 deletions(-)
diff --git a/arch/powerpc/include/asm/book3s/64/pgtable-4k.h b/arch/powerpc/include/asm/book3s/64/pgtable-4k.h
index 71e9abced493..9db83b4e017d 100644
--- a/arch/powerpc/include/asm/book3s/64/pgtable-4k.h
+++ b/arch/powerpc/include/asm/book3s/64/pgtable-4k.h
@@ -11,7 +11,7 @@ static inline int pmd_huge(pmd_t pmd)
* leaf pte for huge page
*/
if (radix_enabled())
- return !!(pmd_val(pmd) & _PAGE_PTE);
+ return !!(pmd_raw(pmd) & cpu_to_be64(_PAGE_PTE));
return 0;
}
@@ -21,7 +21,7 @@ static inline int pud_huge(pud_t pud)
* leaf pte for huge page
*/
if (radix_enabled())
- return !!(pud_val(pud) & _PAGE_PTE);
+ return !!(pud_raw(pud) & cpu_to_be64(_PAGE_PTE));
return 0;
}
@@ -31,7 +31,7 @@ static inline int pgd_huge(pgd_t pgd)
* leaf pte for huge page
*/
if (radix_enabled())
- return !!(pgd_val(pgd) & _PAGE_PTE);
+ return !!(pgd_raw(pgd) & cpu_to_be64(_PAGE_PTE));
return 0;
}
#define pgd_huge pgd_huge
diff --git a/arch/powerpc/include/asm/book3s/64/pgtable-64k.h b/arch/powerpc/include/asm/book3s/64/pgtable-64k.h
index cb2d0a5fa3f8..0d2845b44763 100644
--- a/arch/powerpc/include/asm/book3s/64/pgtable-64k.h
+++ b/arch/powerpc/include/asm/book3s/64/pgtable-64k.h
@@ -15,7 +15,7 @@ static inline int pmd_huge(pmd_t pmd)
/*
* leaf pte for huge page
*/
- return !!(pmd_val(pmd) & _PAGE_PTE);
+ return !!(pmd_raw(pmd) & cpu_to_be64(_PAGE_PTE));
}
static inline int pud_huge(pud_t pud)
@@ -23,7 +23,7 @@ static inline int pud_huge(pud_t pud)
/*
* leaf pte for huge page
*/
- return !!(pud_val(pud) & _PAGE_PTE);
+ return !!(pud_raw(pud) & cpu_to_be64(_PAGE_PTE));
}
static inline int pgd_huge(pgd_t pgd)
@@ -31,7 +31,7 @@ static inline int pgd_huge(pgd_t pgd)
/*
* leaf pte for huge page
*/
- return !!(pgd_val(pgd) & _PAGE_PTE);
+ return !!(pgd_raw(pgd) & cpu_to_be64(_PAGE_PTE));
}
#define pgd_huge pgd_huge
diff --git a/arch/powerpc/include/asm/book3s/64/pgtable.h b/arch/powerpc/include/asm/book3s/64/pgtable.h
index 88a5ecaa157b..d3ab97e3c744 100644
--- a/arch/powerpc/include/asm/book3s/64/pgtable.h
+++ b/arch/powerpc/include/asm/book3s/64/pgtable.h
@@ -317,7 +317,7 @@ static inline int __ptep_test_and_clear_young(struct mm_struct *mm,
{
unsigned long old;
- if ((pte_val(*ptep) & (_PAGE_ACCESSED | H_PAGE_HASHPTE)) == 0)
+ if ((pte_raw(*ptep) & cpu_to_be64(_PAGE_ACCESSED | H_PAGE_HASHPTE)) == 0)
return 0;
old = pte_update(mm, addr, ptep, _PAGE_ACCESSED, 0, 0);
return (old & _PAGE_ACCESSED) != 0;
@@ -335,8 +335,7 @@ static inline int __ptep_test_and_clear_young(struct mm_struct *mm,
static inline void ptep_set_wrprotect(struct mm_struct *mm, unsigned long addr,
pte_t *ptep)
{
-
- if ((pte_val(*ptep) & _PAGE_WRITE) == 0)
+ if ((pte_raw(*ptep) & cpu_to_be64(_PAGE_WRITE)) == 0)
return;
pte_update(mm, addr, ptep, _PAGE_WRITE, 0, 0);
@@ -345,7 +344,7 @@ static inline void ptep_set_wrprotect(struct mm_struct *mm, unsigned long addr,
static inline void huge_ptep_set_wrprotect(struct mm_struct *mm,
unsigned long addr, pte_t *ptep)
{
- if ((pte_val(*ptep) & _PAGE_WRITE) == 0)
+ if ((pte_raw(*ptep) & cpu_to_be64(_PAGE_WRITE)) == 0)
return;
pte_update(mm, addr, ptep, _PAGE_WRITE, 0, 1);
@@ -364,17 +363,35 @@ static inline void pte_clear(struct mm_struct *mm, unsigned long addr,
{
pte_update(mm, addr, ptep, ~0UL, 0, 0);
}
-static inline int pte_write(pte_t pte) { return !!(pte_val(pte) & _PAGE_WRITE);}
-static inline int pte_dirty(pte_t pte) { return !!(pte_val(pte) & _PAGE_DIRTY); }
-static inline int pte_young(pte_t pte) { return !!(pte_val(pte) & _PAGE_ACCESSED); }
-static inline int pte_special(pte_t pte) { return !!(pte_val(pte) & _PAGE_SPECIAL); }
+
+static inline int pte_write(pte_t pte)
+{
+ return !!(pte_raw(pte) & cpu_to_be64(_PAGE_WRITE));
+}
+
+static inline int pte_dirty(pte_t pte)
+{
+ return !!(pte_raw(pte) & cpu_to_be64(_PAGE_DIRTY));
+}
+
+static inline int pte_young(pte_t pte)
+{
+ return !!(pte_raw(pte) & cpu_to_be64(_PAGE_ACCESSED));
+}
+
+static inline int pte_special(pte_t pte)
+{
+ return !!(pte_raw(pte) & cpu_to_be64(_PAGE_SPECIAL));
+}
+
static inline pgprot_t pte_pgprot(pte_t pte) { return __pgprot(pte_val(pte) & PAGE_PROT_BITS); }
#ifdef CONFIG_HAVE_ARCH_SOFT_DIRTY
static inline bool pte_soft_dirty(pte_t pte)
{
- return !!(pte_val(pte) & _PAGE_SOFT_DIRTY);
+ return !!(pte_raw(pte) & cpu_to_be64(_PAGE_SOFT_DIRTY));
}
+
static inline pte_t pte_mksoft_dirty(pte_t pte)
{
return __pte(pte_val(pte) | _PAGE_SOFT_DIRTY);
@@ -394,14 +411,14 @@ static inline pte_t pte_clear_soft_dirty(pte_t pte)
*/
static inline int pte_protnone(pte_t pte)
{
- return (pte_val(pte) & (_PAGE_PRESENT | _PAGE_PRIVILEGED)) ==
- (_PAGE_PRESENT | _PAGE_PRIVILEGED);
+ return (pte_raw(pte) & cpu_to_be64(_PAGE_PRESENT | _PAGE_PRIVILEGED)) ==
+ cpu_to_be64(_PAGE_PRESENT | _PAGE_PRIVILEGED);
}
#endif /* CONFIG_NUMA_BALANCING */
static inline int pte_present(pte_t pte)
{
- return !!(pte_val(pte) & _PAGE_PRESENT);
+ return !!(pte_raw(pte) & cpu_to_be64(_PAGE_PRESENT));
}
/*
* Conversion functions: convert a page and protection to a page entry,
@@ -473,7 +490,7 @@ static inline pte_t pte_modify(pte_t pte, pgprot_t newprot)
static inline bool pte_user(pte_t pte)
{
- return !(pte_val(pte) & _PAGE_PRIVILEGED);
+ return !(pte_raw(pte) & cpu_to_be64(_PAGE_PRIVILEGED));
}
/* Encode and de-code a swap entry */
@@ -516,10 +533,12 @@ static inline pte_t pte_swp_mksoft_dirty(pte_t pte)
{
return __pte(pte_val(pte) | _PAGE_SWP_SOFT_DIRTY);
}
+
static inline bool pte_swp_soft_dirty(pte_t pte)
{
- return !!(pte_val(pte) & _PAGE_SWP_SOFT_DIRTY);
+ return !!(pte_raw(pte) & cpu_to_be64(_PAGE_SWP_SOFT_DIRTY));
}
+
static inline pte_t pte_swp_clear_soft_dirty(pte_t pte)
{
return __pte(pte_val(pte) & ~_PAGE_SWP_SOFT_DIRTY);
@@ -625,8 +644,16 @@ static inline void pmd_clear(pmd_t *pmdp)
*pmdp = __pmd(0);
}
-#define pmd_none(pmd) (!pmd_val(pmd))
-#define pmd_present(pmd) (!pmd_none(pmd))
+static inline int pmd_none(pmd_t pmd)
+{
+ return !pmd_raw(pmd);
+}
+
+static inline int pmd_present(pmd_t pmd)
+{
+
+ return !pmd_none(pmd);
+}
static inline int pmd_bad(pmd_t pmd)
{
@@ -645,19 +672,26 @@ static inline void pud_clear(pud_t *pudp)
*pudp = __pud(0);
}
-#define pud_none(pud) (!pud_val(pud))
-#define pud_present(pud) (pud_val(pud) != 0)
+static inline int pud_none(pud_t pud)
+{
+ return !pud_raw(pud);
+}
+
+static inline int pud_present(pud_t pud)
+{
+ return !pud_none(pud);
+}
extern struct page *pud_page(pud_t pud);
extern struct page *pmd_page(pmd_t pmd);
static inline pte_t pud_pte(pud_t pud)
{
- return __pte(pud_val(pud));
+ return __pte_raw(pud_raw(pud));
}
static inline pud_t pte_pud(pte_t pte)
{
- return __pud(pte_val(pte));
+ return __pud_raw(pte_raw(pte));
}
#define pud_write(pud) pte_write(pud_pte(pud))
@@ -680,17 +714,24 @@ static inline void pgd_clear(pgd_t *pgdp)
*pgdp = __pgd(0);
}
-#define pgd_none(pgd) (!pgd_val(pgd))
-#define pgd_present(pgd) (!pgd_none(pgd))
+static inline int pgd_none(pgd_t pgd)
+{
+ return !pgd_raw(pgd);
+}
+
+static inline int pgd_present(pgd_t pgd)
+{
+ return !pgd_none(pgd);
+}
static inline pte_t pgd_pte(pgd_t pgd)
{
- return __pte(pgd_val(pgd));
+ return __pte_raw(pgd_raw(pgd));
}
static inline pgd_t pte_pgd(pte_t pte)
{
- return __pgd(pte_val(pte));
+ return __pgd_raw(pte_raw(pte));
}
static inline int pgd_bad(pgd_t pgd)
@@ -782,12 +823,12 @@ struct page *realmode_pfn_to_page(unsigned long pfn);
static inline pte_t pmd_pte(pmd_t pmd)
{
- return __pte(pmd_val(pmd));
+ return __pte_raw(pmd_raw(pmd));
}
static inline pmd_t pte_pmd(pte_t pte)
{
- return __pmd(pte_val(pte));
+ return __pmd_raw(pte_raw(pte));
}
static inline pte_t *pmdp_ptep(pmd_t *pmd)
@@ -848,7 +889,7 @@ pmd_hugepage_update(struct mm_struct *mm, unsigned long addr, pmd_t *pmdp,
static inline int pmd_large(pmd_t pmd)
{
- return !!(pmd_val(pmd) & _PAGE_PTE);
+ return !!(pmd_raw(pmd) & cpu_to_be64(_PAGE_PTE));
}
static inline pmd_t pmd_mknotpresent(pmd_t pmd)
@@ -864,7 +905,7 @@ static inline int __pmdp_test_and_clear_young(struct mm_struct *mm,
{
unsigned long old;
- if ((pmd_val(*pmdp) & (_PAGE_ACCESSED | H_PAGE_HASHPTE)) == 0)
+ if ((pmd_raw(*pmdp) & cpu_to_be64(_PAGE_ACCESSED | H_PAGE_HASHPTE)) == 0)
return 0;
old = pmd_hugepage_update(mm, addr, pmdp, _PAGE_ACCESSED, 0);
return ((old & _PAGE_ACCESSED) != 0);
@@ -875,7 +916,7 @@ static inline void pmdp_set_wrprotect(struct mm_struct *mm, unsigned long addr,
pmd_t *pmdp)
{
- if ((pmd_val(*pmdp) & _PAGE_WRITE) == 0)
+ if ((pmd_raw(*pmdp) & cpu_to_be64(_PAGE_WRITE)) == 0)
return;
pmd_hugepage_update(mm, addr, pmdp, _PAGE_WRITE, 0);
diff --git a/arch/powerpc/include/asm/pgtable-be-types.h b/arch/powerpc/include/asm/pgtable-be-types.h
index e2bf208605b1..49c0a5a80efa 100644
--- a/arch/powerpc/include/asm/pgtable-be-types.h
+++ b/arch/powerpc/include/asm/pgtable-be-types.h
@@ -6,6 +6,7 @@
/* PTE level */
typedef struct { __be64 pte; } pte_t;
#define __pte(x) ((pte_t) { cpu_to_be64(x) })
+#define __pte_raw(x) ((pte_t) { (x) })
static inline unsigned long pte_val(pte_t x)
{
return be64_to_cpu(x.pte);
@@ -20,6 +21,7 @@ static inline __be64 pte_raw(pte_t x)
#ifdef CONFIG_PPC64
typedef struct { __be64 pmd; } pmd_t;
#define __pmd(x) ((pmd_t) { cpu_to_be64(x) })
+#define __pmd_raw(x) ((pmd_t) { (x) })
static inline unsigned long pmd_val(pmd_t x)
{
return be64_to_cpu(x.pmd);
@@ -37,21 +39,34 @@ static inline __be64 pmd_raw(pmd_t x)
#if defined(CONFIG_PPC_BOOK3S_64) || !defined(CONFIG_PPC_64K_PAGES)
typedef struct { __be64 pud; } pud_t;
#define __pud(x) ((pud_t) { cpu_to_be64(x) })
+#define __pud_raw(x) ((pud_t) { (x) })
static inline unsigned long pud_val(pud_t x)
{
return be64_to_cpu(x.pud);
}
+
+static inline __be64 pud_raw(pud_t x)
+{
+ return x.pud;
+}
+
#endif /* CONFIG_PPC_BOOK3S_64 || !CONFIG_PPC_64K_PAGES */
#endif /* CONFIG_PPC64 */
/* PGD level */
typedef struct { __be64 pgd; } pgd_t;
#define __pgd(x) ((pgd_t) { cpu_to_be64(x) })
+#define __pgd_raw(x) ((pgd_t) { (x) })
static inline unsigned long pgd_val(pgd_t x)
{
return be64_to_cpu(x.pgd);
}
+static inline __be64 pgd_raw(pgd_t x)
+{
+ return x.pgd;
+}
+
/* Page protection bits */
typedef struct { unsigned long pgprot; } pgprot_t;
#define pgprot_val(x) ((x).pgprot)
--
2.7.4
^ permalink raw reply related [flat|nested] 24+ messages in thread* Re: [PATCH for-4.8 03/12] powerpc/mm: use _raw variant of page table accessors
2016-07-13 9:35 ` [PATCH for-4.8 03/12] powerpc/mm: use _raw variant of page table accessors Aneesh Kumar K.V
@ 2016-07-14 3:42 ` Balbir Singh
2016-07-15 11:42 ` David Laight
1 sibling, 0 replies; 24+ messages in thread
From: Balbir Singh @ 2016-07-14 3:42 UTC (permalink / raw)
To: Aneesh Kumar K.V; +Cc: benh, paulus, mpe, linuxppc-dev
On Wed, Jul 13, 2016 at 03:05:22PM +0530, Aneesh Kumar K.V wrote:
> This switch few of the page table accessor to use the __raw variant
^^ switches ^^ accessors
> and does the cpu to big endian conversion of constants. This helps in
> generating better code.
>
> For ex: a pgd_none(pgd) check with and without fix is listed below
>
> Without fix:
> ------------
> 2240: 20 00 61 eb ld r27,32(r1)
> /* PGD level */
> typedef struct { __be64 pgd; } pgd_t;
> static inline unsigned long pgd_val(pgd_t x)
> {
> return be64_to_cpu(x.pgd);
>
> 2244: 22 00 66 78 rldicl r6,r3,32,32
> 2248: 3e 40 7d 54 rotlwi r29,r3,8
> 224c: 0e c0 7d 50 rlwimi r29,r3,24,0,7
> 2250: 3e 40 c5 54 rotlwi r5,r6,8
> 2254: 2e c4 7d 50 rlwimi r29,r3,24,16,23
> 2258: 0e c0 c5 50 rlwimi r5,r6,24,0,7
> 225c: 2e c4 c5 50 rlwimi r5,r6,24,16,23
> 2260: c6 07 bd 7b rldicr r29,r29,32,31
> 2264: 78 2b bd 7f or r29,r29,r5
> if (pgd_none(pgd))
> 2268: 00 00 bd 2f cmpdi cr7,r29,0
> 226c: 54 03 9e 41 beq cr7,25c0 <__get_user_pages_fast+0x500>
>
> With fix:
> ---------
> 2370: 20 00 61 eb ld r27,32(r1)
> if (pgd_none(pgd))
> 2374: 00 00 bd 2f cmpdi cr7,r29,0
> 2378: a8 03 9e 41 beq cr7,2720 <__get_user_pages_fast+0x530>
> break;
> Signed-off-by: Aneesh Kumar K.V <aneesh.kumar@linux.vnet.ibm.com>
> ---
Acked-by: Balbir Singh <bsingharora@gmail.com>
^ permalink raw reply [flat|nested] 24+ messages in thread* RE: [PATCH for-4.8 03/12] powerpc/mm: use _raw variant of page table accessors
2016-07-13 9:35 ` [PATCH for-4.8 03/12] powerpc/mm: use _raw variant of page table accessors Aneesh Kumar K.V
2016-07-14 3:42 ` Balbir Singh
@ 2016-07-15 11:42 ` David Laight
2016-07-17 5:22 ` Anton Blanchard
1 sibling, 1 reply; 24+ messages in thread
From: David Laight @ 2016-07-15 11:42 UTC (permalink / raw)
To: 'Aneesh Kumar K.V', benh@kernel.crashing.org,
paulus@samba.org, mpe@ellerman.id.au
Cc: linuxppc-dev@lists.ozlabs.org
RnJvbTogQW5lZXNoIEt1bWFyIEsuVg0KPiBTZW50OiAxMyBKdWx5IDIwMTYgMTA6MzUNCj4gDQo+
IFRoaXMgc3dpdGNoIGZldyBvZiB0aGUgcGFnZSB0YWJsZSBhY2Nlc3NvciB0byB1c2UgdGhlIF9f
cmF3IHZhcmlhbnQNCj4gYW5kIGRvZXMgdGhlIGNwdSB0byBiaWcgZW5kaWFuIGNvbnZlcnNpb24g
b2YgY29uc3RhbnRzLiBUaGlzIGhlbHBzIGluDQo+IGdlbmVyYXRpbmcgYmV0dGVyIGNvZGUuDQoN
Ckl0IG1pZ2h0IGJlIGJldHRlciB0byBzYXkgdGhhdCBjaGVja3MgZm9yIGEgdmFsdWUgYmVpbmcg
MCBkb24ndCBkZXBlbmQNCm9uIHRoZSBlbmRpYW5uZXNzLg0KDQpJbiB3aGljaCBjYXNlIHlvdSB3
YW50IGEgZnVuY3Rpb24gdGhhdCByZXR1cm4gISF4eHhfcmF3KCkgaXRzZWxmLg0KDQpPVE9IIGl0
IG1pZ2h0IGJlIHdvcnRoIGZpbmRpbmcgb3V0IHdoeSB0aGUgY3B1J3MgYnl0ZXN3YXBwaW5nIG1l
bW9yeQ0KYWNjZXNzb3JzIGFyZW4ndCB1c2VkIC0gd2hpY2ggbWlnaHQgc2F2ZSB0aGUgYnl0ZXN3
YXAgaW5zdHJ1Y3Rpb24NCnNlcXVlbmNlIGluIGFsbCBwYXRocy4NCg0KCURhdmlkDQoNCg==
^ permalink raw reply [flat|nested] 24+ messages in thread
* Re: [PATCH for-4.8 03/12] powerpc/mm: use _raw variant of page table accessors
2016-07-15 11:42 ` David Laight
@ 2016-07-17 5:22 ` Anton Blanchard
0 siblings, 0 replies; 24+ messages in thread
From: Anton Blanchard @ 2016-07-17 5:22 UTC (permalink / raw)
To: David Laight
Cc: 'Aneesh Kumar K.V', benh@kernel.crashing.org,
paulus@samba.org, mpe@ellerman.id.au,
linuxppc-dev@lists.ozlabs.org
Hi David,
> > This switch few of the page table accessor to use the __raw variant
> > and does the cpu to big endian conversion of constants. This helps
> > in generating better code.
>
> It might be better to say that checks for a value being 0 don't depend
> on the endianness.
>
> In which case you want a function that return !!xxx_raw() itself.
>
> OTOH it might be worth finding out why the cpu's byteswapping memory
> accessors aren't used - which might save the byteswap instruction
> sequence in all paths.
There was a discussion about this on the list. In short, we found a
couple of reasons. Accesses often use READ_ONCE() which might cause
problems. The bigger issue is if the pte is accessed via larx/stcx. We
have no byte reversed larx/stcx instructions.
Anton
^ permalink raw reply [flat|nested] 24+ messages in thread
* [PATCH for-4.8 04/12] powerpc/mm: Compile out radix related functions if RADIX_MMU is disabled
2016-07-13 9:35 [PATCH for-4.8_set1 00/12] Radix fixes for 4.8 Aneesh Kumar K.V
` (2 preceding siblings ...)
2016-07-13 9:35 ` [PATCH for-4.8 03/12] powerpc/mm: use _raw variant of page table accessors Aneesh Kumar K.V
@ 2016-07-13 9:35 ` Aneesh Kumar K.V
2016-07-13 9:35 ` [PATCH for-4.8 05/12] powerpc/mm: Clear top 16 bits of va only on older cpus Aneesh Kumar K.V
` (7 subsequent siblings)
11 siblings, 0 replies; 24+ messages in thread
From: Aneesh Kumar K.V @ 2016-07-13 9:35 UTC (permalink / raw)
To: benh, paulus, mpe; +Cc: linuxppc-dev, Aneesh Kumar K.V
Currently we depend on mmu_has_feature to evalute to zero based on
MMU_FTRS_POSSIBLE mask. In a later patch, we want to update
radix_enabled() to runtime update the conditional operation to a jump
instruction. This implies we cannot depend on MMU_FTRS_POSSIBLE mask.
Instead define radix_enabled to return 0 if RADIX_MMU is not enabled.
Signed-off-by: Aneesh Kumar K.V <aneesh.kumar@linux.vnet.ibm.com>
---
arch/powerpc/include/asm/book3s/64/mmu.h | 5 +++++
1 file changed, 5 insertions(+)
diff --git a/arch/powerpc/include/asm/book3s/64/mmu.h b/arch/powerpc/include/asm/book3s/64/mmu.h
index 5854263d4d6e..d4eda6420523 100644
--- a/arch/powerpc/include/asm/book3s/64/mmu.h
+++ b/arch/powerpc/include/asm/book3s/64/mmu.h
@@ -23,7 +23,12 @@ struct mmu_psize_def {
};
extern struct mmu_psize_def mmu_psize_defs[MMU_PAGE_COUNT];
+#ifdef CONFIG_PPC_RADIX_MMU
#define radix_enabled() mmu_has_feature(MMU_FTR_RADIX)
+#else
+#define radix_enabled() (0)
+#endif
+
#endif /* __ASSEMBLY__ */
--
2.7.4
^ permalink raw reply related [flat|nested] 24+ messages in thread* [PATCH for-4.8 05/12] powerpc/mm: Clear top 16 bits of va only on older cpus
2016-07-13 9:35 [PATCH for-4.8_set1 00/12] Radix fixes for 4.8 Aneesh Kumar K.V
` (3 preceding siblings ...)
2016-07-13 9:35 ` [PATCH for-4.8 04/12] powerpc/mm: Compile out radix related functions if RADIX_MMU is disabled Aneesh Kumar K.V
@ 2016-07-13 9:35 ` Aneesh Kumar K.V
2016-07-14 3:50 ` Balbir Singh
2016-07-13 9:35 ` [PATCH for-4.8 06/12] powerpc/mm: Print formation regarding the the MMU mode Aneesh Kumar K.V
` (6 subsequent siblings)
11 siblings, 1 reply; 24+ messages in thread
From: Aneesh Kumar K.V @ 2016-07-13 9:35 UTC (permalink / raw)
To: benh, paulus, mpe; +Cc: linuxppc-dev, Aneesh Kumar K.V
As per ISA, we need to do this only for architecture version 2.02 and
earlier. This continued to work even for 2.07. But let's not do this for
anything after 2.02. ISA 3.0 requires these top bits to be not cleared.
Signed-off-by: Aneesh Kumar K.V <aneesh.kumar@linux.vnet.ibm.com>
---
arch/powerpc/include/asm/mmu.h | 9 +++++++--
arch/powerpc/kernel/cputable.c | 4 ++--
arch/powerpc/mm/hash_native_64.c | 6 ++++--
3 files changed, 13 insertions(+), 6 deletions(-)
diff --git a/arch/powerpc/include/asm/mmu.h b/arch/powerpc/include/asm/mmu.h
index e53ebebff474..54471228f7b8 100644
--- a/arch/powerpc/include/asm/mmu.h
+++ b/arch/powerpc/include/asm/mmu.h
@@ -24,6 +24,11 @@
/*
* This is individual features
*/
+/*
+ * We need to clear top 16bits of va (from the remaining 64 bits )in
+ * tlbie* instructions
+ */
+#define MMU_FTR_TLBIE_CROP_VA ASM_CONST(0x00008000)
/* Enable use of high BAT registers */
#define MMU_FTR_USE_HIGH_BATS ASM_CONST(0x00010000)
@@ -97,7 +102,7 @@
#define MMU_FTRS_DEFAULT_HPTE_ARCH_V2 \
MMU_FTR_HPTE_TABLE | MMU_FTR_PPCAS_ARCH_V2
#define MMU_FTRS_POWER4 MMU_FTRS_DEFAULT_HPTE_ARCH_V2
-#define MMU_FTRS_PPC970 MMU_FTRS_POWER4
+#define MMU_FTRS_PPC970 MMU_FTRS_POWER4 | MMU_FTR_TLBIE_CROP_VA
#define MMU_FTRS_POWER5 MMU_FTRS_POWER4 | MMU_FTR_LOCKLESS_TLBIE
#define MMU_FTRS_POWER6 MMU_FTRS_POWER4 | MMU_FTR_LOCKLESS_TLBIE
#define MMU_FTRS_POWER7 MMU_FTRS_POWER4 | MMU_FTR_LOCKLESS_TLBIE
@@ -124,7 +129,7 @@ enum {
MMU_FTR_USE_TLBRSRV | MMU_FTR_USE_PAIRED_MAS |
MMU_FTR_NO_SLBIE_B | MMU_FTR_16M_PAGE | MMU_FTR_TLBIEL |
MMU_FTR_LOCKLESS_TLBIE | MMU_FTR_CI_LARGE_PAGE |
- MMU_FTR_1T_SEGMENT |
+ MMU_FTR_1T_SEGMENT | MMU_FTR_TLBIE_CROP_VA |
#ifdef CONFIG_PPC_RADIX_MMU
MMU_FTR_RADIX |
#endif
diff --git a/arch/powerpc/kernel/cputable.c b/arch/powerpc/kernel/cputable.c
index eeeacf6235a3..d81f826d1029 100644
--- a/arch/powerpc/kernel/cputable.c
+++ b/arch/powerpc/kernel/cputable.c
@@ -137,7 +137,7 @@ static struct cpu_spec __initdata cpu_specs[] = {
.cpu_name = "POWER4 (gp)",
.cpu_features = CPU_FTRS_POWER4,
.cpu_user_features = COMMON_USER_POWER4,
- .mmu_features = MMU_FTRS_POWER4,
+ .mmu_features = MMU_FTRS_POWER4 | MMU_FTR_TLBIE_CROP_VA,
.icache_bsize = 128,
.dcache_bsize = 128,
.num_pmcs = 8,
@@ -152,7 +152,7 @@ static struct cpu_spec __initdata cpu_specs[] = {
.cpu_name = "POWER4+ (gq)",
.cpu_features = CPU_FTRS_POWER4,
.cpu_user_features = COMMON_USER_POWER4,
- .mmu_features = MMU_FTRS_POWER4,
+ .mmu_features = MMU_FTRS_POWER4 | MMU_FTR_TLBIE_CROP_VA,
.icache_bsize = 128,
.dcache_bsize = 128,
.num_pmcs = 8,
diff --git a/arch/powerpc/mm/hash_native_64.c b/arch/powerpc/mm/hash_native_64.c
index b0e0fdbe0273..70521ef171fc 100644
--- a/arch/powerpc/mm/hash_native_64.c
+++ b/arch/powerpc/mm/hash_native_64.c
@@ -64,7 +64,8 @@ static inline void __tlbie(unsigned long vpn, int psize, int apsize, int ssize)
* Older versions of the architecture (2.02 and earler) require the
* masking of the top 16 bits.
*/
- va &= ~(0xffffULL << 48);
+ if (mmu_has_feature(MMU_FTR_TLBIE_CROP_VA))
+ va &= ~(0xffffULL << 48);
switch (psize) {
case MMU_PAGE_4K:
@@ -113,7 +114,8 @@ static inline void __tlbiel(unsigned long vpn, int psize, int apsize, int ssize)
* Older versions of the architecture (2.02 and earler) require the
* masking of the top 16 bits.
*/
- va &= ~(0xffffULL << 48);
+ if (mmu_has_feature(MMU_FTR_TLBIE_CROP_VA))
+ va &= ~(0xffffULL << 48);
switch (psize) {
case MMU_PAGE_4K:
--
2.7.4
^ permalink raw reply related [flat|nested] 24+ messages in thread* [PATCH for-4.8 06/12] powerpc/mm: Print formation regarding the the MMU mode
2016-07-13 9:35 [PATCH for-4.8_set1 00/12] Radix fixes for 4.8 Aneesh Kumar K.V
` (4 preceding siblings ...)
2016-07-13 9:35 ` [PATCH for-4.8 05/12] powerpc/mm: Clear top 16 bits of va only on older cpus Aneesh Kumar K.V
@ 2016-07-13 9:35 ` Aneesh Kumar K.V
2016-07-14 4:03 ` Balbir Singh
2016-07-13 9:35 ` [PATCH for-4.8 07/12] powerpc/mm/hash: Update SDR1 size encoding as documented in ISA 3.0 Aneesh Kumar K.V
` (5 subsequent siblings)
11 siblings, 1 reply; 24+ messages in thread
From: Aneesh Kumar K.V @ 2016-07-13 9:35 UTC (permalink / raw)
To: benh, paulus, mpe; +Cc: linuxppc-dev, Aneesh Kumar K.V
This helps in easily identifying the MMU mode with which the kernel
is operating.
Signed-off-by: Aneesh Kumar K.V <aneesh.kumar@linux.vnet.ibm.com>
---
arch/powerpc/mm/hash_utils_64.c | 3 ++-
arch/powerpc/mm/pgtable-radix.c | 3 ++-
2 files changed, 4 insertions(+), 2 deletions(-)
diff --git a/arch/powerpc/mm/hash_utils_64.c b/arch/powerpc/mm/hash_utils_64.c
index 7e6d38e01645..b90fe2480089 100644
--- a/arch/powerpc/mm/hash_utils_64.c
+++ b/arch/powerpc/mm/hash_utils_64.c
@@ -739,7 +739,7 @@ static void __init hash_init_partition_table(phys_addr_t hash_table,
* For now UPRT is 0 for us.
*/
partition_tb->patb1 = 0;
- DBG("Partition table %p\n", partition_tb);
+ pr_info("Partition table %p\n", partition_tb);
/*
* update partition table control register,
* 64 K size.
@@ -943,6 +943,7 @@ void __init hash__early_init_mmu(void)
*/
htab_initialize();
+ pr_info("Initializing hash mmu with SLB\n");
/* Initialize SLB management */
slb_initialize();
}
diff --git a/arch/powerpc/mm/pgtable-radix.c b/arch/powerpc/mm/pgtable-radix.c
index f8a3bec315f7..366d1ea24465 100644
--- a/arch/powerpc/mm/pgtable-radix.c
+++ b/arch/powerpc/mm/pgtable-radix.c
@@ -182,7 +182,8 @@ static void __init radix_init_partition_table(void)
partition_tb = early_alloc_pgtable(1UL << PATB_SIZE_SHIFT);
partition_tb->patb0 = cpu_to_be64(rts_field | __pa(init_mm.pgd) |
RADIX_PGD_INDEX_SIZE | PATB_HR);
- printk("Partition table %p\n", partition_tb);
+ pr_info("Initializing Radix MMU\n");
+ pr_info("Partition table %p\n", partition_tb);
memblock_set_current_limit(MEMBLOCK_ALLOC_ANYWHERE);
/*
--
2.7.4
^ permalink raw reply related [flat|nested] 24+ messages in thread* Re: [PATCH for-4.8 06/12] powerpc/mm: Print formation regarding the the MMU mode
2016-07-13 9:35 ` [PATCH for-4.8 06/12] powerpc/mm: Print formation regarding the the MMU mode Aneesh Kumar K.V
@ 2016-07-14 4:03 ` Balbir Singh
0 siblings, 0 replies; 24+ messages in thread
From: Balbir Singh @ 2016-07-14 4:03 UTC (permalink / raw)
To: Aneesh Kumar K.V; +Cc: benh, paulus, mpe, linuxppc-dev
On Wed, Jul 13, 2016 at 03:05:25PM +0530, Aneesh Kumar K.V wrote:
> This helps in easily identifying the MMU mode with which the kernel
> is operating.
>
> Signed-off-by: Aneesh Kumar K.V <aneesh.kumar@linux.vnet.ibm.com>
> ---
> arch/powerpc/mm/hash_utils_64.c | 3 ++-
> arch/powerpc/mm/pgtable-radix.c | 3 ++-
> 2 files changed, 4 insertions(+), 2 deletions(-)
>
> diff --git a/arch/powerpc/mm/hash_utils_64.c b/arch/powerpc/mm/hash_utils_64.c
> index 7e6d38e01645..b90fe2480089 100644
> --- a/arch/powerpc/mm/hash_utils_64.c
> +++ b/arch/powerpc/mm/hash_utils_64.c
> @@ -739,7 +739,7 @@ static void __init hash_init_partition_table(phys_addr_t hash_table,
> * For now UPRT is 0 for us.
> */
> partition_tb->patb1 = 0;
> - DBG("Partition table %p\n", partition_tb);
> + pr_info("Partition table %p\n", partition_tb);
> /*
> * update partition table control register,
> * 64 K size.
> @@ -943,6 +943,7 @@ void __init hash__early_init_mmu(void)
> */
> htab_initialize();
>
> + pr_info("Initializing hash mmu with SLB\n");
Can we be consistent and use Hash MMU like for Radix MMU below
Balbir Singh
^ permalink raw reply [flat|nested] 24+ messages in thread
* [PATCH for-4.8 07/12] powerpc/mm/hash: Update SDR1 size encoding as documented in ISA 3.0
2016-07-13 9:35 [PATCH for-4.8_set1 00/12] Radix fixes for 4.8 Aneesh Kumar K.V
` (5 preceding siblings ...)
2016-07-13 9:35 ` [PATCH for-4.8 06/12] powerpc/mm: Print formation regarding the the MMU mode Aneesh Kumar K.V
@ 2016-07-13 9:35 ` Aneesh Kumar K.V
2016-07-14 4:29 ` Balbir Singh
2016-07-13 9:35 ` [PATCH for-4.8 08/12] powerpc/mm/radix: Update PID switch sequence Aneesh Kumar K.V
` (4 subsequent siblings)
11 siblings, 1 reply; 24+ messages in thread
From: Aneesh Kumar K.V @ 2016-07-13 9:35 UTC (permalink / raw)
To: benh, paulus, mpe; +Cc: linuxppc-dev, Aneesh Kumar K.V
ISA 3.0 document hash table size in bytes = 2^(HTABSIZE + 18)
No functionality change by this patch.
Signed-off-by: Aneesh Kumar K.V <aneesh.kumar@linux.vnet.ibm.com>
---
arch/powerpc/mm/hash_utils_64.c | 9 ++++-----
1 file changed, 4 insertions(+), 5 deletions(-)
diff --git a/arch/powerpc/mm/hash_utils_64.c b/arch/powerpc/mm/hash_utils_64.c
index b90fe2480089..47d59a1f12f1 100644
--- a/arch/powerpc/mm/hash_utils_64.c
+++ b/arch/powerpc/mm/hash_utils_64.c
@@ -714,10 +714,9 @@ int remove_section_mapping(unsigned long start, unsigned long end)
#endif /* CONFIG_MEMORY_HOTPLUG */
static void __init hash_init_partition_table(phys_addr_t hash_table,
- unsigned long pteg_count)
+ unsigned long htab_size)
{
unsigned long ps_field;
- unsigned long htab_size;
unsigned long patb_size = 1UL << PATB_SIZE_SHIFT;
/*
@@ -725,7 +724,7 @@ static void __init hash_init_partition_table(phys_addr_t hash_table,
* We can ignore that for lpid 0
*/
ps_field = 0;
- htab_size = __ilog2(pteg_count) - 11;
+ htab_size = __ilog2(htab_size) - 18;
BUILD_BUG_ON_MSG((PATB_SIZE_SHIFT > 24), "Partition table size too large.");
partition_tb = __va(memblock_alloc_base(patb_size, patb_size,
@@ -811,7 +810,7 @@ static void __init htab_initialize(void)
htab_address = __va(table);
/* htab absolute addr + encoded htabsize */
- _SDR1 = table + __ilog2(pteg_count) - 11;
+ _SDR1 = table + __ilog2(htab_size_bytes) - 18;
/* Initialize the HPT with no entries */
memset((void *)table, 0, htab_size_bytes);
@@ -820,7 +819,7 @@ static void __init htab_initialize(void)
/* Set SDR1 */
mtspr(SPRN_SDR1, _SDR1);
else
- hash_init_partition_table(table, pteg_count);
+ hash_init_partition_table(table, htab_size_bytes);
}
prot = pgprot_val(PAGE_KERNEL);
--
2.7.4
^ permalink raw reply related [flat|nested] 24+ messages in thread* Re: [PATCH for-4.8 07/12] powerpc/mm/hash: Update SDR1 size encoding as documented in ISA 3.0
2016-07-13 9:35 ` [PATCH for-4.8 07/12] powerpc/mm/hash: Update SDR1 size encoding as documented in ISA 3.0 Aneesh Kumar K.V
@ 2016-07-14 4:29 ` Balbir Singh
0 siblings, 0 replies; 24+ messages in thread
From: Balbir Singh @ 2016-07-14 4:29 UTC (permalink / raw)
To: Aneesh Kumar K.V; +Cc: benh, paulus, mpe, linuxppc-dev
On Wed, Jul 13, 2016 at 03:05:26PM +0530, Aneesh Kumar K.V wrote:
> ISA 3.0 document hash table size in bytes = 2^(HTABSIZE + 18)
>
> No functionality change by this patch.
>
> Signed-off-by: Aneesh Kumar K.V <aneesh.kumar@linux.vnet.ibm.com>
> ---
> arch/powerpc/mm/hash_utils_64.c | 9 ++++-----
> 1 file changed, 4 insertions(+), 5 deletions(-)
>
> diff --git a/arch/powerpc/mm/hash_utils_64.c b/arch/powerpc/mm/hash_utils_64.c
> index b90fe2480089..47d59a1f12f1 100644
> --- a/arch/powerpc/mm/hash_utils_64.c
> +++ b/arch/powerpc/mm/hash_utils_64.c
> @@ -714,10 +714,9 @@ int remove_section_mapping(unsigned long start, unsigned long end)
> #endif /* CONFIG_MEMORY_HOTPLUG */
>
> static void __init hash_init_partition_table(phys_addr_t hash_table,
> - unsigned long pteg_count)
> + unsigned long htab_size)
> {
> unsigned long ps_field;
> - unsigned long htab_size;
> unsigned long patb_size = 1UL << PATB_SIZE_SHIFT;
>
> /*
> @@ -725,7 +724,7 @@ static void __init hash_init_partition_table(phys_addr_t hash_table,
> * We can ignore that for lpid 0
> */
> ps_field = 0;
> - htab_size = __ilog2(pteg_count) - 11;
> + htab_size = __ilog2(htab_size) - 18;
I was wondering if we should just do
#define HPT_MIN_SIZE_SHIFT 18
and then use it instead?
^ permalink raw reply [flat|nested] 24+ messages in thread
* [PATCH for-4.8 08/12] powerpc/mm/radix: Update PID switch sequence
2016-07-13 9:35 [PATCH for-4.8_set1 00/12] Radix fixes for 4.8 Aneesh Kumar K.V
` (6 preceding siblings ...)
2016-07-13 9:35 ` [PATCH for-4.8 07/12] powerpc/mm/hash: Update SDR1 size encoding as documented in ISA 3.0 Aneesh Kumar K.V
@ 2016-07-13 9:35 ` Aneesh Kumar K.V
2016-07-13 9:35 ` [PATCH for-4.8 09/12] powerpc/mm/radix: Update machine call back to support new HCALL Aneesh Kumar K.V
` (3 subsequent siblings)
11 siblings, 0 replies; 24+ messages in thread
From: Aneesh Kumar K.V @ 2016-07-13 9:35 UTC (permalink / raw)
To: benh, paulus, mpe; +Cc: linuxppc-dev, Aneesh Kumar K.V
Update the PID switch as per ISA doc. slbia is needed in radix to
invalidate any implementation specific lookaside information.
We use the .long format due to build errors with the below compiler
version.
gcc (Ubuntu 5.3.1-14ubuntu2.1) 5.3.1 20160413
GNU assembler (GNU Binutils for Ubuntu) 2.26
CC arch/powerpc/mm//mmu_context_book3s64.o
{standard input}: Assembler messages:
{standard input}:506: Error: junk at end of line: `0x7'
scripts/Makefile.build:291: recipe for target 'arch/powerpc/mm//mmu_context_book3s64.o' failed
make[1]: *** [arch/powerpc/mm//mmu_context_book3s64.o] Error 1
Signed-off-by: Aneesh Kumar K.V <aneesh.kumar@linux.vnet.ibm.com>
---
arch/powerpc/include/asm/ppc-opcode.h | 3 +++
arch/powerpc/mm/mmu_context_book3s64.c | 5 ++++-
2 files changed, 7 insertions(+), 1 deletion(-)
diff --git a/arch/powerpc/include/asm/ppc-opcode.h b/arch/powerpc/include/asm/ppc-opcode.h
index 1c9b1d4386ba..27b81302fb36 100644
--- a/arch/powerpc/include/asm/ppc-opcode.h
+++ b/arch/powerpc/include/asm/ppc-opcode.h
@@ -181,6 +181,7 @@
#define PPC_INST_MTSPR_DSCR_USER 0x7c0303a6
#define PPC_INST_MTSPR_DSCR_USER_MASK 0xfc1fffff
#define PPC_INST_SLBFEE 0x7c0007a7
+#define PPC_INST_SLBIA 0x7c0003e4
#define PPC_INST_STRING 0x7c00042a
#define PPC_INST_STRING_MASK 0xfc0007fe
@@ -438,5 +439,7 @@
___PPC_RA(a) | \
___PPC_RB(b))
+#define PPC_SLBIA(IH) stringify_in_c(.long PPC_INST_SLBIA | \
+ ((IH & 0x7) << 21))
#endif /* _ASM_POWERPC_PPC_OPCODE_H */
diff --git a/arch/powerpc/mm/mmu_context_book3s64.c b/arch/powerpc/mm/mmu_context_book3s64.c
index 196222227e82..b114f8b93ec9 100644
--- a/arch/powerpc/mm/mmu_context_book3s64.c
+++ b/arch/powerpc/mm/mmu_context_book3s64.c
@@ -181,7 +181,10 @@ void destroy_context(struct mm_struct *mm)
#ifdef CONFIG_PPC_RADIX_MMU
void radix__switch_mmu_context(struct mm_struct *prev, struct mm_struct *next)
{
- mtspr(SPRN_PID, next->context.id);
asm volatile("isync": : :"memory");
+ mtspr(SPRN_PID, next->context.id);
+ asm volatile("isync \n"
+ PPC_SLBIA(0x7)
+ : : :"memory");
}
#endif
--
2.7.4
^ permalink raw reply related [flat|nested] 24+ messages in thread* [PATCH for-4.8 09/12] powerpc/mm/radix: Update machine call back to support new HCALL.
2016-07-13 9:35 [PATCH for-4.8_set1 00/12] Radix fixes for 4.8 Aneesh Kumar K.V
` (7 preceding siblings ...)
2016-07-13 9:35 ` [PATCH for-4.8 08/12] powerpc/mm/radix: Update PID switch sequence Aneesh Kumar K.V
@ 2016-07-13 9:35 ` Aneesh Kumar K.V
2016-07-13 9:35 ` [PATCH for-4.8 10/12] powerpc/mm/radix: Add LPID based tlb flush helpers Aneesh Kumar K.V
` (2 subsequent siblings)
11 siblings, 0 replies; 24+ messages in thread
From: Aneesh Kumar K.V @ 2016-07-13 9:35 UTC (permalink / raw)
To: benh, paulus, mpe; +Cc: linuxppc-dev, Aneesh Kumar K.V
This update the machine dep callback such that we can use the same
callback to register process table. The interface is updated such that
we can easily call H_REGISTER_PROC_TBL hcall. The HCALL itself is
introduced in a later patch.
No functionality change introduced by this patch.
Signed-off-by: Aneesh Kumar K.V <aneesh.kumar@linux.vnet.ibm.com>
---
arch/powerpc/include/asm/machdep.h | 3 ++-
arch/powerpc/mm/hash_native_64.c | 10 ++++++++--
arch/powerpc/mm/pgtable-radix.c | 9 ++++++---
3 files changed, 16 insertions(+), 6 deletions(-)
diff --git a/arch/powerpc/include/asm/machdep.h b/arch/powerpc/include/asm/machdep.h
index 6bdcd0da9e21..4c8260855748 100644
--- a/arch/powerpc/include/asm/machdep.h
+++ b/arch/powerpc/include/asm/machdep.h
@@ -256,7 +256,8 @@ struct machdep_calls {
#ifdef CONFIG_ARCH_RANDOM
int (*get_random_seed)(unsigned long *v);
#endif
- int (*update_partition_table)(u64);
+ int (*register_process_table)(unsigned long base, unsigned long page_size,
+ unsigned long tbl_size);
};
extern void e500_idle(void);
diff --git a/arch/powerpc/mm/hash_native_64.c b/arch/powerpc/mm/hash_native_64.c
index 70521ef171fc..cb3b4c98b637 100644
--- a/arch/powerpc/mm/hash_native_64.c
+++ b/arch/powerpc/mm/hash_native_64.c
@@ -725,8 +725,14 @@ static void native_flush_hash_range(unsigned long number, int local)
local_irq_restore(flags);
}
-static int native_update_partition_table(u64 patb1)
+static int native_register_proc_table(unsigned long base, unsigned long page_size,
+ unsigned long table_size)
{
+ unsigned long patb1 = base << 25; /* VSID */
+
+ patb1 |= (page_size << 5); /* sllp */
+ patb1 |= table_size;
+
partition_tb->patb1 = cpu_to_be64(patb1);
return 0;
}
@@ -743,5 +749,5 @@ void __init hpte_init_native(void)
ppc_md.hugepage_invalidate = native_hugepage_invalidate;
if (cpu_has_feature(CPU_FTR_ARCH_300))
- ppc_md.update_partition_table = native_update_partition_table;
+ ppc_md.register_process_table = native_register_proc_table;
}
diff --git a/arch/powerpc/mm/pgtable-radix.c b/arch/powerpc/mm/pgtable-radix.c
index 366d1ea24465..ce21a0f2c2a1 100644
--- a/arch/powerpc/mm/pgtable-radix.c
+++ b/arch/powerpc/mm/pgtable-radix.c
@@ -21,8 +21,11 @@
#include <trace/events/thp.h>
-static int native_update_partition_table(u64 patb1)
+static int native_register_process_table(unsigned long base, unsigned long pg_sz,
+ unsigned long table_size)
{
+ unsigned long patb1 = base | table_size | PATB_GR;
+
partition_tb->patb1 = cpu_to_be64(patb1);
return 0;
}
@@ -168,7 +171,7 @@ redo:
* of process table here. But our linear mapping also enable us to use
* physical address here.
*/
- ppc_md.update_partition_table(__pa(process_tb) | (PRTB_SIZE_SHIFT - 12) | PATB_GR);
+ ppc_md.register_process_table(__pa(process_tb), 0, PRTB_SIZE_SHIFT - 12);
pr_info("Process table %p and radix root for kernel: %p\n", process_tb, init_mm.pgd);
}
@@ -195,7 +198,7 @@ static void __init radix_init_partition_table(void)
void __init radix_init_native(void)
{
- ppc_md.update_partition_table = native_update_partition_table;
+ ppc_md.register_process_table = native_register_process_table;
}
static int __init get_idx_from_shift(unsigned int shift)
--
2.7.4
^ permalink raw reply related [flat|nested] 24+ messages in thread* [PATCH for-4.8 10/12] powerpc/mm/radix: Add LPID based tlb flush helpers
2016-07-13 9:35 [PATCH for-4.8_set1 00/12] Radix fixes for 4.8 Aneesh Kumar K.V
` (8 preceding siblings ...)
2016-07-13 9:35 ` [PATCH for-4.8 09/12] powerpc/mm/radix: Update machine call back to support new HCALL Aneesh Kumar K.V
@ 2016-07-13 9:35 ` Aneesh Kumar K.V
2016-07-14 5:12 ` Balbir Singh
2016-07-13 9:35 ` [PATCH for-4.8 11/12] powerpc/mm: Cleanup LPCR defines Aneesh Kumar K.V
2016-07-13 9:35 ` [PATCH for-4.8 12/12] powerpc/mm/radix: Add a kernel command line to disable radix Aneesh Kumar K.V
11 siblings, 1 reply; 24+ messages in thread
From: Aneesh Kumar K.V @ 2016-07-13 9:35 UTC (permalink / raw)
To: benh, paulus, mpe; +Cc: linuxppc-dev, Aneesh Kumar K.V
We add a tlb flush variant, to flush LPID mappings.
Signed-off-by: Aneesh Kumar K.V <aneesh.kumar@linux.vnet.ibm.com>
---
.../powerpc/include/asm/book3s/64/tlbflush-radix.h | 4 +-
arch/powerpc/mm/tlb-radix.c | 52 ++++++++++++++++++++++
2 files changed, 55 insertions(+), 1 deletion(-)
diff --git a/arch/powerpc/include/asm/book3s/64/tlbflush-radix.h b/arch/powerpc/include/asm/book3s/64/tlbflush-radix.h
index 3fa94fcac628..00703e7e4c94 100644
--- a/arch/powerpc/include/asm/book3s/64/tlbflush-radix.h
+++ b/arch/powerpc/include/asm/book3s/64/tlbflush-radix.h
@@ -32,5 +32,7 @@ extern void radix__flush_tlb_pwc(struct mmu_gather *tlb, unsigned long addr);
#define radix___flush_tlb_page(mm,addr,p,i) radix___local_flush_tlb_page(mm,addr,p,i)
#define radix__flush_tlb_pwc(tlb, addr) radix__local_flush_tlb_pwc(tlb, addr)
#endif
-
+extern void radix__flush_tlb_lpid_va(unsigned long lpid, unsigned long gpa,
+ unsigned long page_size);
+extern void radix__flush_tlb_lpid(unsigned long lpid);
#endif
diff --git a/arch/powerpc/mm/tlb-radix.c b/arch/powerpc/mm/tlb-radix.c
index 35690c41f85d..e1f22700fb16 100644
--- a/arch/powerpc/mm/tlb-radix.c
+++ b/arch/powerpc/mm/tlb-radix.c
@@ -282,9 +282,61 @@ void radix__flush_tlb_range(struct vm_area_struct *vma, unsigned long start,
}
EXPORT_SYMBOL(radix__flush_tlb_range);
+static int radix_get_mmu_psize(int page_size)
+{
+ int psize;
+
+ if (page_size == (1UL << mmu_psize_defs[mmu_virtual_psize].shift))
+ psize = mmu_virtual_psize;
+ else if (page_size == (1UL << mmu_psize_defs[MMU_PAGE_2M].shift))
+ psize = MMU_PAGE_2M;
+ else if (page_size == (1UL << mmu_psize_defs[MMU_PAGE_1G].shift))
+ psize = MMU_PAGE_1G;
+ else
+ return -1;
+ return psize;
+}
void radix__tlb_flush(struct mmu_gather *tlb)
{
struct mm_struct *mm = tlb->mm;
radix__flush_tlb_mm(mm);
}
+
+void radix__flush_tlb_lpid_va(unsigned long lpid, unsigned long gpa,
+ unsigned long page_size)
+{
+ unsigned long rb,rs,prs,r;
+ unsigned long ap;
+ unsigned long ric = RIC_FLUSH_TLB;
+
+ ap = mmu_get_ap(radix_get_mmu_psize(page_size));
+ rb = gpa & ~(PPC_BITMASK(52, 63));
+ rb |= ap << PPC_BITLSHIFT(58);
+ rs = lpid & ((1UL << 32) - 1);
+ prs = 0; /* process scoped */
+ r = 1; /* raidx format */
+
+ asm volatile("ptesync": : :"memory");
+ asm volatile(PPC_TLBIE_5(%0, %4, %3, %2, %1)
+ : : "r"(rb), "i"(r), "i"(prs), "i"(ric), "r"(rs) : "memory");
+ asm volatile("eieio; tlbsync; ptesync": : :"memory");
+}
+EXPORT_SYMBOL(radix__flush_tlb_lpid_va);
+
+void radix__flush_tlb_lpid(unsigned long lpid)
+{
+ unsigned long rb,rs,prs,r;
+ unsigned long ric = RIC_FLUSH_ALL;
+
+ rb = 0x2 << PPC_BITLSHIFT(53); /* IS = 2 */
+ rs = lpid & ((1UL << 32) - 1);
+ prs = 0; /* partition scoped */
+ r = 1; /* raidx format */
+
+ asm volatile("ptesync": : :"memory");
+ asm volatile(PPC_TLBIE_5(%0, %4, %3, %2, %1)
+ : : "r"(rb), "i"(r), "i"(prs), "i"(ric), "r"(rs) : "memory");
+ asm volatile("eieio; tlbsync; ptesync": : :"memory");
+}
+EXPORT_SYMBOL(radix__flush_tlb_lpid);
--
2.7.4
^ permalink raw reply related [flat|nested] 24+ messages in thread* Re: [PATCH for-4.8 10/12] powerpc/mm/radix: Add LPID based tlb flush helpers
2016-07-13 9:35 ` [PATCH for-4.8 10/12] powerpc/mm/radix: Add LPID based tlb flush helpers Aneesh Kumar K.V
@ 2016-07-14 5:12 ` Balbir Singh
0 siblings, 0 replies; 24+ messages in thread
From: Balbir Singh @ 2016-07-14 5:12 UTC (permalink / raw)
To: Aneesh Kumar K.V; +Cc: benh, paulus, mpe, linuxppc-dev
On Wed, Jul 13, 2016 at 03:05:29PM +0530, Aneesh Kumar K.V wrote:
> We add a tlb flush variant, to flush LPID mappings.
>
> Signed-off-by: Aneesh Kumar K.V <aneesh.kumar@linux.vnet.ibm.com>
> ---
> .../powerpc/include/asm/book3s/64/tlbflush-radix.h | 4 +-
> arch/powerpc/mm/tlb-radix.c | 52 ++++++++++++++++++++++
> 2 files changed, 55 insertions(+), 1 deletion(-)
>
> diff --git a/arch/powerpc/include/asm/book3s/64/tlbflush-radix.h b/arch/powerpc/include/asm/book3s/64/tlbflush-radix.h
> index 3fa94fcac628..00703e7e4c94 100644
> --- a/arch/powerpc/include/asm/book3s/64/tlbflush-radix.h
> +++ b/arch/powerpc/include/asm/book3s/64/tlbflush-radix.h
> @@ -32,5 +32,7 @@ extern void radix__flush_tlb_pwc(struct mmu_gather *tlb, unsigned long addr);
> #define radix___flush_tlb_page(mm,addr,p,i) radix___local_flush_tlb_page(mm,addr,p,i)
> #define radix__flush_tlb_pwc(tlb, addr) radix__local_flush_tlb_pwc(tlb, addr)
> #endif
> -
> +extern void radix__flush_tlb_lpid_va(unsigned long lpid, unsigned long gpa,
> + unsigned long page_size);
> +extern void radix__flush_tlb_lpid(unsigned long lpid);
> #endif
> diff --git a/arch/powerpc/mm/tlb-radix.c b/arch/powerpc/mm/tlb-radix.c
> index 35690c41f85d..e1f22700fb16 100644
> --- a/arch/powerpc/mm/tlb-radix.c
> +++ b/arch/powerpc/mm/tlb-radix.c
> @@ -282,9 +282,61 @@ void radix__flush_tlb_range(struct vm_area_struct *vma, unsigned long start,
> }
> EXPORT_SYMBOL(radix__flush_tlb_range);
>
> +static int radix_get_mmu_psize(int page_size)
> +{
> + int psize;
> +
> + if (page_size == (1UL << mmu_psize_defs[mmu_virtual_psize].shift))
> + psize = mmu_virtual_psize;
> + else if (page_size == (1UL << mmu_psize_defs[MMU_PAGE_2M].shift))
> + psize = MMU_PAGE_2M;
> + else if (page_size == (1UL << mmu_psize_defs[MMU_PAGE_1G].shift))
> + psize = MMU_PAGE_1G;
> + else
> + return -1;
Just do psize = -1;
> + return psize;
> +}
>
> void radix__tlb_flush(struct mmu_gather *tlb)
> {
> struct mm_struct *mm = tlb->mm;
> radix__flush_tlb_mm(mm);
> }
> +
> +void radix__flush_tlb_lpid_va(unsigned long lpid, unsigned long gpa,
> + unsigned long page_size)
> +{
> + unsigned long rb,rs,prs,r;
> + unsigned long ap;
> + unsigned long ric = RIC_FLUSH_TLB;
> +
> + ap = mmu_get_ap(radix_get_mmu_psize(page_size));
> + rb = gpa & ~(PPC_BITMASK(52, 63));
> + rb |= ap << PPC_BITLSHIFT(58);
> + rs = lpid & ((1UL << 32) - 1);
> + prs = 0; /* process scoped */
> + r = 1; /* raidx format */
> +
> + asm volatile("ptesync": : :"memory");
> + asm volatile(PPC_TLBIE_5(%0, %4, %3, %2, %1)
> + : : "r"(rb), "i"(r), "i"(prs), "i"(ric), "r"(rs) : "memory");
> + asm volatile("eieio; tlbsync; ptesync": : :"memory");
> +}
> +EXPORT_SYMBOL(radix__flush_tlb_lpid_va);
> +
> +void radix__flush_tlb_lpid(unsigned long lpid)
> +{
> + unsigned long rb,rs,prs,r;
> + unsigned long ric = RIC_FLUSH_ALL;
> +
> + rb = 0x2 << PPC_BITLSHIFT(53); /* IS = 2 */
> + rs = lpid & ((1UL << 32) - 1);
> + prs = 0; /* partition scoped */
> + r = 1; /* raidx format */
> +
> + asm volatile("ptesync": : :"memory");
> + asm volatile(PPC_TLBIE_5(%0, %4, %3, %2, %1)
> + : : "r"(rb), "i"(r), "i"(prs), "i"(ric), "r"(rs) : "memory");
> + asm volatile("eieio; tlbsync; ptesync": : :"memory");
> +}
> +EXPORT_SYMBOL(radix__flush_tlb_lpid);
^ permalink raw reply [flat|nested] 24+ messages in thread
* [PATCH for-4.8 11/12] powerpc/mm: Cleanup LPCR defines
2016-07-13 9:35 [PATCH for-4.8_set1 00/12] Radix fixes for 4.8 Aneesh Kumar K.V
` (9 preceding siblings ...)
2016-07-13 9:35 ` [PATCH for-4.8 10/12] powerpc/mm/radix: Add LPID based tlb flush helpers Aneesh Kumar K.V
@ 2016-07-13 9:35 ` Aneesh Kumar K.V
2016-07-13 9:35 ` [PATCH for-4.8 12/12] powerpc/mm/radix: Add a kernel command line to disable radix Aneesh Kumar K.V
11 siblings, 0 replies; 24+ messages in thread
From: Aneesh Kumar K.V @ 2016-07-13 9:35 UTC (permalink / raw)
To: benh, paulus, mpe; +Cc: linuxppc-dev, Aneesh Kumar K.V
This makes it easy to verify we are not overloading the bits.
No functionality change by this patch.
Signed-off-by: Aneesh Kumar K.V <aneesh.kumar@linux.vnet.ibm.com>
---
arch/powerpc/include/asm/reg.h | 56 +++++++++++++++++++++---------------------
1 file changed, 28 insertions(+), 28 deletions(-)
diff --git a/arch/powerpc/include/asm/reg.h b/arch/powerpc/include/asm/reg.h
index a5ba263e0353..a69e8f3a4171 100644
--- a/arch/powerpc/include/asm/reg.h
+++ b/arch/powerpc/include/asm/reg.h
@@ -319,42 +319,42 @@
#define HFSCR_FP __MASK(FSCR_FP_LG)
#define SPRN_TAR 0x32f /* Target Address Register */
#define SPRN_LPCR 0x13E /* LPAR Control Register */
-#define LPCR_VPM0 (1ul << (63-0))
-#define LPCR_VPM1 (1ul << (63-1))
-#define LPCR_ISL (1ul << (63-2))
+#define LPCR_VPM0 ASM_CONST(0x8000000000000000)
+#define LPCR_VPM1 ASM_CONST(0x4000000000000000)
+#define LPCR_ISL ASM_CONST(0x2000000000000000)
#define LPCR_VC_SH (63-2)
#define LPCR_DPFD_SH (63-11)
#define LPCR_DPFD (7ul << LPCR_DPFD_SH)
#define LPCR_VRMASD (0x1ful << (63-16))
-#define LPCR_VRMA_L (1ul << (63-12))
-#define LPCR_VRMA_LP0 (1ul << (63-15))
-#define LPCR_VRMA_LP1 (1ul << (63-16))
+#define LPCR_VRMA_L ASM_CONST(0x0008000000000000)
+#define LPCR_VRMA_LP0 ASM_CONST(0x0001000000000000)
+#define LPCR_VRMA_LP1 ASM_CONST(0x0000800000000000)
#define LPCR_VRMASD_SH (63-16)
-#define LPCR_RMLS 0x1C000000 /* impl dependent rmo limit sel */
+#define LPCR_RMLS 0x1C000000 /* impl dependent rmo limit sel */
#define LPCR_RMLS_SH (63-37)
-#define LPCR_ILE 0x02000000 /* !HV irqs set MSR:LE */
-#define LPCR_AIL 0x01800000 /* Alternate interrupt location */
-#define LPCR_AIL_0 0x00000000 /* MMU off exception offset 0x0 */
-#define LPCR_AIL_3 0x01800000 /* MMU on exception offset 0xc00...4xxx */
-#define LPCR_ONL 0x00040000 /* online - PURR/SPURR count */
-#define LPCR_LD 0x00020000 /* large decremeter */
-#define LPCR_PECE 0x0001f000 /* powersave exit cause enable */
-#define LPCR_PECEDP 0x00010000 /* directed priv dbells cause exit */
-#define LPCR_PECEDH 0x00008000 /* directed hyp dbells cause exit */
-#define LPCR_PECE0 0x00004000 /* ext. exceptions can cause exit */
-#define LPCR_PECE1 0x00002000 /* decrementer can cause exit */
-#define LPCR_PECE2 0x00001000 /* machine check etc can cause exit */
-#define LPCR_MER 0x00000800 /* Mediated External Exception */
+#define LPCR_ILE ASM_CONST(0x0000000002000000) /* !HV irqs set MSR:LE */
+#define LPCR_AIL ASM_CONST(0x0000000001800000) /* Alternate interrupt location */
+#define LPCR_AIL_0 ASM_CONST(0x0000000000000000) /* MMU off exception offset 0x0 */
+#define LPCR_AIL_3 ASM_CONST(0x0000000001800000) /* MMU on exception offset 0xc00...4xxx */
+#define LPCR_ONL ASM_CONST(0x0000000000040000) /* online - PURR/SPURR count */
+#define LPCR_LD ASM_CONST(0x0000000000020000) /* large decremeter */
+#define LPCR_PECE ASM_CONST(0x000000000001f000) /* powersave exit cause enable */
+#define LPCR_PECEDP ASM_CONST(0x0000000000010000) /* directed priv dbells cause exit */
+#define LPCR_PECEDH ASM_CONST(0x0000000000008000) /* directed hyp dbells cause exit */
+#define LPCR_PECE0 ASM_CONST(0x0000000000004000) /* ext. exceptions can cause exit */
+#define LPCR_PECE1 ASM_CONST(0x0000000000002000) /* decrementer can cause exit */
+#define LPCR_PECE2 ASM_CONST(0x0000000000001000) /* machine check etc can cause exit */
+#define LPCR_MER ASM_CONST(0x0000000000000800) /* Mediated External Exception */
#define LPCR_MER_SH 11
-#define LPCR_TC 0x00000200 /* Translation control */
-#define LPCR_LPES 0x0000000c
-#define LPCR_LPES0 0x00000008 /* LPAR Env selector 0 */
-#define LPCR_LPES1 0x00000004 /* LPAR Env selector 1 */
+#define LPCR_TC ASM_CONST(0x0000000000000200) /* Translation control */
+#define LPCR_LPES 0x0000000c
+#define LPCR_LPES0 ASM_CONST(0x0000000000000008) /* LPAR Env selector 0 */
+#define LPCR_LPES1 ASM_CONST(0x0000000000000004) /* LPAR Env selector 1 */
#define LPCR_LPES_SH 2
-#define LPCR_RMI 0x00000002 /* real mode is cache inhibit */
-#define LPCR_HDICE 0x00000001 /* Hyp Decr enable (HV,PR,EE) */
-#define LPCR_UPRT 0x00400000 /* Use Process Table (ISA 3) */
-#define LPCR_HR 0x00100000
+#define LPCR_RMI ASM_CONST(0x0000000000000002) /* real mode is cache inhibit */
+#define LPCR_HDICE ASM_CONST(0x0000000000000001) /* Hyp Decr enable (HV,PR,EE) */
+#define LPCR_UPRT ASM_CONST(0x0000000000400000) /* Use Process Table (ISA 3) */
+#define LPCR_HR ASM_CONST(0x0000000000100000)
#ifndef SPRN_LPID
#define SPRN_LPID 0x13F /* Logical Partition Identifier */
#endif
--
2.7.4
^ permalink raw reply related [flat|nested] 24+ messages in thread* [PATCH for-4.8 12/12] powerpc/mm/radix: Add a kernel command line to disable radix
2016-07-13 9:35 [PATCH for-4.8_set1 00/12] Radix fixes for 4.8 Aneesh Kumar K.V
` (10 preceding siblings ...)
2016-07-13 9:35 ` [PATCH for-4.8 11/12] powerpc/mm: Cleanup LPCR defines Aneesh Kumar K.V
@ 2016-07-13 9:35 ` Aneesh Kumar K.V
2016-07-14 5:02 ` Balbir Singh
11 siblings, 1 reply; 24+ messages in thread
From: Aneesh Kumar K.V @ 2016-07-13 9:35 UTC (permalink / raw)
To: benh, paulus, mpe; +Cc: linuxppc-dev, Aneesh Kumar K.V
This patch adds the kernel command line disable_radix which disable
the radix MMU mode even if firmware indicates radix support via
ibm,pa-features device tree node.
This helps in testing different MMU mode easily.
Signed-off-by: Aneesh Kumar K.V <aneesh.kumar@linux.vnet.ibm.com>
---
Documentation/kernel-parameters.txt | 3 +++
arch/powerpc/kernel/prom.c | 13 +++++++++++++
2 files changed, 16 insertions(+)
diff --git a/Documentation/kernel-parameters.txt b/Documentation/kernel-parameters.txt
index 738bae4a5958..bba7ef30d74e 100644
--- a/Documentation/kernel-parameters.txt
+++ b/Documentation/kernel-parameters.txt
@@ -929,6 +929,9 @@ bytes respectively. Such letter suffixes can also be entirely omitted.
disable= [IPV6]
See Documentation/networking/ipv6.txt.
+ disable_radix [PPC]
+ Disable RADIX MMU mode on POWER9
+
disable_cpu_apicid= [X86,APIC,SMP]
Format: <int>
The number of initial APIC ID for the
diff --git a/arch/powerpc/kernel/prom.c b/arch/powerpc/kernel/prom.c
index 946e34ffeae9..022540b9366d 100644
--- a/arch/powerpc/kernel/prom.c
+++ b/arch/powerpc/kernel/prom.c
@@ -645,6 +645,14 @@ static void __init early_reserve_mem(void)
#endif
}
+static bool disable_radix;
+static int __init parse_disable_radix(char *p)
+{
+ disable_radix = true;
+ return 0;
+}
+early_param("disable_radix", parse_disable_radix);
+
void __init early_init_devtree(void *params)
{
phys_addr_t limit;
@@ -739,6 +747,11 @@ void __init early_init_devtree(void *params)
/* Scan and build the list of machine check recoverable ranges */
of_scan_flat_dt(early_init_dt_scan_recoverable_ranges, NULL);
#endif
+ /*
+ * now fixup radix MMU mode based on kernel command line
+ */
+ if (disable_radix)
+ cur_cpu_spec->mmu_features &= ~MMU_FTR_RADIX;
DBG(" <- early_init_devtree()\n");
}
--
2.7.4
^ permalink raw reply related [flat|nested] 24+ messages in thread* Re: [PATCH for-4.8 12/12] powerpc/mm/radix: Add a kernel command line to disable radix
2016-07-13 9:35 ` [PATCH for-4.8 12/12] powerpc/mm/radix: Add a kernel command line to disable radix Aneesh Kumar K.V
@ 2016-07-14 5:02 ` Balbir Singh
2016-07-14 8:43 ` Aneesh Kumar K.V
0 siblings, 1 reply; 24+ messages in thread
From: Balbir Singh @ 2016-07-14 5:02 UTC (permalink / raw)
To: Aneesh Kumar K.V; +Cc: benh, paulus, mpe, linuxppc-dev
On Wed, Jul 13, 2016 at 03:05:31PM +0530, Aneesh Kumar K.V wrote:
> This patch adds the kernel command line disable_radix which disable
> the radix MMU mode even if firmware indicates radix support via
> ibm,pa-features device tree node.
>
> This helps in testing different MMU mode easily.
>
> Signed-off-by: Aneesh Kumar K.V <aneesh.kumar@linux.vnet.ibm.com>
> ---
> Documentation/kernel-parameters.txt | 3 +++
> arch/powerpc/kernel/prom.c | 13 +++++++++++++
> 2 files changed, 16 insertions(+)
>
> diff --git a/Documentation/kernel-parameters.txt b/Documentation/kernel-parameters.txt
> index 738bae4a5958..bba7ef30d74e 100644
> --- a/Documentation/kernel-parameters.txt
> +++ b/Documentation/kernel-parameters.txt
> @@ -929,6 +929,9 @@ bytes respectively. Such letter suffixes can also be entirely omitted.
> disable= [IPV6]
> See Documentation/networking/ipv6.txt.
>
> + disable_radix [PPC]
> + Disable RADIX MMU mode on POWER9
> +
> disable_cpu_apicid= [X86,APIC,SMP]
> Format: <int>
> The number of initial APIC ID for the
> diff --git a/arch/powerpc/kernel/prom.c b/arch/powerpc/kernel/prom.c
> index 946e34ffeae9..022540b9366d 100644
> --- a/arch/powerpc/kernel/prom.c
> +++ b/arch/powerpc/kernel/prom.c
> @@ -645,6 +645,14 @@ static void __init early_reserve_mem(void)
> #endif
> }
>
> +static bool disable_radix;
__read_mostly?
> +static int __init parse_disable_radix(char *p)
> +{
> + disable_radix = true;
> + return 0;
> +}
> +early_param("disable_radix", parse_disable_radix);
> +
> void __init early_init_devtree(void *params)
> {
> phys_addr_t limit;
> @@ -739,6 +747,11 @@ void __init early_init_devtree(void *params)
> /* Scan and build the list of machine check recoverable ranges */
> of_scan_flat_dt(early_init_dt_scan_recoverable_ranges, NULL);
> #endif
> + /*
> + * now fixup radix MMU mode based on kernel command line
> + */
> + if (disable_radix)
> + cur_cpu_spec->mmu_features &= ~MMU_FTR_RADIX;
Shouldn't this happen before prom_init() and exchanging capabilities?
^ permalink raw reply [flat|nested] 24+ messages in thread* Re: [PATCH for-4.8 12/12] powerpc/mm/radix: Add a kernel command line to disable radix
2016-07-14 5:02 ` Balbir Singh
@ 2016-07-14 8:43 ` Aneesh Kumar K.V
0 siblings, 0 replies; 24+ messages in thread
From: Aneesh Kumar K.V @ 2016-07-14 8:43 UTC (permalink / raw)
To: bsingharora; +Cc: benh, paulus, mpe, linuxppc-dev
Balbir Singh <bsingharora@gmail.com> writes:
> On Wed, Jul 13, 2016 at 03:05:31PM +0530, Aneesh Kumar K.V wrote:
>> This patch adds the kernel command line disable_radix which disable
>> the radix MMU mode even if firmware indicates radix support via
>> ibm,pa-features device tree node.
>>
>> This helps in testing different MMU mode easily.
>>
>> Signed-off-by: Aneesh Kumar K.V <aneesh.kumar@linux.vnet.ibm.com>
>> ---
>> Documentation/kernel-parameters.txt | 3 +++
>> arch/powerpc/kernel/prom.c | 13 +++++++++++++
>> 2 files changed, 16 insertions(+)
>>
>> diff --git a/Documentation/kernel-parameters.txt b/Documentation/kernel-parameters.txt
>> index 738bae4a5958..bba7ef30d74e 100644
>> --- a/Documentation/kernel-parameters.txt
>> +++ b/Documentation/kernel-parameters.txt
>> @@ -929,6 +929,9 @@ bytes respectively. Such letter suffixes can also be entirely omitted.
>> disable= [IPV6]
>> See Documentation/networking/ipv6.txt.
>>
>> + disable_radix [PPC]
>> + Disable RADIX MMU mode on POWER9
>> +
>> disable_cpu_apicid= [X86,APIC,SMP]
>> Format: <int>
>> The number of initial APIC ID for the
>> diff --git a/arch/powerpc/kernel/prom.c b/arch/powerpc/kernel/prom.c
>> index 946e34ffeae9..022540b9366d 100644
>> --- a/arch/powerpc/kernel/prom.c
>> +++ b/arch/powerpc/kernel/prom.c
>> @@ -645,6 +645,14 @@ static void __init early_reserve_mem(void)
>> #endif
>> }
>>
>> +static bool disable_radix;
>
> __read_mostly?
We actually read it only once.
>
>> +static int __init parse_disable_radix(char *p)
>> +{
>> + disable_radix = true;
>> + return 0;
>> +}
>> +early_param("disable_radix", parse_disable_radix);
>> +
>> void __init early_init_devtree(void *params)
>> {
>> phys_addr_t limit;
>> @@ -739,6 +747,11 @@ void __init early_init_devtree(void *params)
>> /* Scan and build the list of machine check recoverable ranges */
>> of_scan_flat_dt(early_init_dt_scan_recoverable_ranges, NULL);
>> #endif
>> + /*
>> + * now fixup radix MMU mode based on kernel command line
>> + */
>> + if (disable_radix)
>> + cur_cpu_spec->mmu_features &= ~MMU_FTR_RADIX;
>
> Shouldn't this happen before prom_init() and exchanging capabilities?
Didn't get that. We actually set the FTR_RADIX in
check_cpu_pa_features(node) which is called via
of_scan_flat_dt(early_init_dt_scan_cpus, NULL); We clear that
immediately after if the feature is disabled via kernel command line.
-aneesh
^ permalink raw reply [flat|nested] 24+ messages in thread