From: Paul Mackerras <paulus@ozlabs.org>
To: "Aneesh Kumar K.V" <aneesh.kumar@linux.vnet.ibm.com>
Cc: kvm@vger.kernel.org, kvm-ppc@vger.kernel.org, linuxppc-dev@ozlabs.org
Subject: Re: [PATCH 09/13] KVM: PPC: Book3S HV: Adapt TLB invalidations to work on POWER9
Date: Sat, 19 Nov 2016 15:13:12 +1100 [thread overview]
Message-ID: <20161119041312.GD29462@fergus.ozlabs.ibm.com> (raw)
In-Reply-To: <87y40gn941.fsf@linux.vnet.ibm.com>
On Fri, Nov 18, 2016 at 08:11:34PM +0530, Aneesh Kumar K.V wrote:
> > @@ -3287,6 +3290,17 @@ static int kvmppc_core_init_vm_hv(struct kvm *kvm)
> > kvm->arch.lpcr = lpcr;
> >
> > /*
> > + * Work out how many sets the TLB has, for the use of
> > + * the TLB invalidation loop in book3s_hv_rmhandlers.S.
> > + */
> > + if (cpu_has_feature(CPU_FTR_ARCH_300))
> > + kvm->arch.tlb_sets = 256; /* POWER9 */
> > + else if (cpu_has_feature(CPU_FTR_ARCH_207S))
> > + kvm->arch.tlb_sets = 512; /* POWER8 */
> > + else
> > + kvm->arch.tlb_sets = 128; /* POWER7 */
> > +
>
> We have
>
> #define POWER7_TLB_SETS 128 /* # sets in POWER7 TLB */
> #define POWER8_TLB_SETS 512 /* # sets in POWER8 TLB */
> #define POWER9_TLB_SETS_HASH 256 /* # sets in POWER9 TLB Hash mode */
> #define POWER9_TLB_SETS_RADIX 128 /* # sets in POWER9 TLB Radix mode */
>
> May be use that instead of opencoding ?
Doing that would make it easier to check that we're using the same
values everywhere but harder to see what actual numbers we're
getting. I guess I could use the symbols and put the values in the
comments. In any case, in future these values are just going to be
default values if we can't find a suitable device-tree property.
Paul.
next prev parent reply other threads:[~2016-11-19 4:23 UTC|newest]
Thread overview: 32+ messages / expand[flat|nested] mbox.gz Atom feed top
2016-11-18 7:28 [PATCH 00/13] KVM: PPC: Support POWER9 guests Paul Mackerras
2016-11-18 7:28 ` [PATCH 01/13] powerpc/64: Add some more SPRs and SPR bits for POWER9 Paul Mackerras
2016-11-18 7:28 ` [PATCH 02/13] powerpc/64: Provide functions for accessing POWER9 partition table Paul Mackerras
2016-11-18 14:27 ` Aneesh Kumar K.V
2016-11-19 4:19 ` Paul Mackerras
2016-11-19 6:35 ` Aneesh Kumar K.V
2016-11-21 2:14 ` Paul Mackerras
2016-11-19 0:45 ` Balbir Singh
2016-11-19 4:23 ` Paul Mackerras
2016-11-18 7:28 ` [PATCH 03/13] powerpc/powernv: Define real-mode versions of OPAL XICS accessors Paul Mackerras
2016-11-18 7:28 ` [PATCH 04/13] KVM: PPC: Book3S HV: Don't lose hardware R/C bit updates in H_PROTECT Paul Mackerras
2016-11-18 7:28 ` [PATCH 05/13] KVM: PPC: Book3S HV: Adapt to new HPTE format on POWER9 Paul Mackerras
2016-11-19 0:38 ` Balbir Singh
2016-11-21 2:02 ` Paul Mackerras
2016-11-18 7:28 ` [PATCH 06/13] KVM: PPC: Book3S HV: Set partition table rather than SDR1 " Paul Mackerras
2016-11-19 1:01 ` Balbir Singh
2016-11-18 7:28 ` [PATCH 07/13] KVM: PPC: Book3S HV: Adjust host/guest context switch for POWER9 Paul Mackerras
2016-11-18 14:35 ` Aneesh Kumar K.V
2016-11-19 4:02 ` Paul Mackerras
2016-11-18 7:28 ` [PATCH 08/13] KVM: PPC: Book3S HV: Add new POWER9 guest-accessible SPRs Paul Mackerras
2016-11-18 7:28 ` [PATCH 09/13] KVM: PPC: Book3S HV: Adapt TLB invalidations to work on POWER9 Paul Mackerras
2016-11-18 14:41 ` Aneesh Kumar K.V
2016-11-18 21:57 ` Benjamin Herrenschmidt
2016-11-19 4:14 ` Paul Mackerras
2016-11-19 4:41 ` Benjamin Herrenschmidt
2016-11-19 4:13 ` Paul Mackerras [this message]
2016-11-18 7:28 ` [PATCH 10/13] KVM: PPC: Book3S HV: Use msgsnd for IPIs to other cores " Paul Mackerras
2016-11-18 14:47 ` Aneesh Kumar K.V
2016-11-19 3:53 ` Paul Mackerras
2016-11-18 7:28 ` [PATCH 11/13] KVM: PPC: Book3S HV: Use OPAL XICS emulation " Paul Mackerras
2016-11-18 7:28 ` [PATCH 12/13] KVM: PPC: Book3S HV: Use stop instruction rather than nap " Paul Mackerras
2016-11-18 7:28 ` [PATCH 13/13] KVM: PPC: Book3S HV: Treat POWER9 CPU threads as independent subcores Paul Mackerras
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