From: "Aneesh Kumar K.V" <aneesh.kumar@linux.vnet.ibm.com>
To: benh@kernel.crashing.org, paulus@samba.org, mpe@ellerman.id.au
Cc: linuxppc-dev@lists.ozlabs.org,
"Aneesh Kumar K.V" <aneesh.kumar@linux.vnet.ibm.com>
Subject: [PATCH v7 2/7] powerpc/mm/hugetlb: Handle hugepage size supported by hash config
Date: Mon, 28 Nov 2016 11:46:59 +0530 [thread overview]
Message-ID: <20161128061704.4914-3-aneesh.kumar@linux.vnet.ibm.com> (raw)
In-Reply-To: <20161128061704.4914-1-aneesh.kumar@linux.vnet.ibm.com>
W.r.t hash page table config, we support 16MB and 16GB as the hugepage
size. Update the hstate_get_psize to handle 16M and 16G.
Signed-off-by: Aneesh Kumar K.V <aneesh.kumar@linux.vnet.ibm.com>
---
arch/powerpc/include/asm/book3s/64/hugetlb.h | 4 ++++
1 file changed, 4 insertions(+)
diff --git a/arch/powerpc/include/asm/book3s/64/hugetlb.h b/arch/powerpc/include/asm/book3s/64/hugetlb.h
index 499268045306..d9c283f95e05 100644
--- a/arch/powerpc/include/asm/book3s/64/hugetlb.h
+++ b/arch/powerpc/include/asm/book3s/64/hugetlb.h
@@ -21,6 +21,10 @@ static inline int hstate_get_psize(struct hstate *hstate)
return MMU_PAGE_2M;
else if (shift == mmu_psize_defs[MMU_PAGE_1G].shift)
return MMU_PAGE_1G;
+ else if (shift == mmu_psize_defs[MMU_PAGE_16M].shift)
+ return MMU_PAGE_16M;
+ else if (shift == mmu_psize_defs[MMU_PAGE_16G].shift)
+ return MMU_PAGE_16G;
else {
WARN(1, "Wrong huge page shift\n");
return mmu_virtual_psize;
--
2.10.2
next prev parent reply other threads:[~2016-11-28 6:17 UTC|newest]
Thread overview: 17+ messages / expand[flat|nested] mbox.gz Atom feed top
2016-11-28 6:16 [PATCH v7 0/7] Radix pte update tlbflush optimizations Aneesh Kumar K.V
2016-11-28 6:16 ` [PATCH v7 1/7] powerpc/mm: Rename hugetlb-radix.h to hugetlb.h Aneesh Kumar K.V
2016-11-29 11:33 ` Balbir Singh
2016-11-29 12:58 ` [v7,1/7] " Michael Ellerman
2016-11-28 6:16 ` Aneesh Kumar K.V [this message]
2016-11-29 11:35 ` [PATCH v7 2/7] powerpc/mm/hugetlb: Handle hugepage size supported by hash config Balbir Singh
2016-11-28 6:17 ` [PATCH v7 3/7] powerpc/mm: Introduce _PAGE_LARGE software pte bits Aneesh Kumar K.V
2016-11-30 0:14 ` Balbir Singh
2016-11-30 0:35 ` Benjamin Herrenschmidt
2016-11-30 0:50 ` Balbir Singh
2016-11-28 6:17 ` [PATCH v7 4/7] powerpc/mm: Add radix__tlb_flush_pte Aneesh Kumar K.V
2016-11-28 11:42 ` Michael Ellerman
2016-11-28 6:17 ` [PATCH v7 5/7] powerpc/mm: update radix__ptep_set_access_flag to not do full mm tlb flush Aneesh Kumar K.V
2016-11-28 6:17 ` [PATCH v7 6/7] powerpc/mm: update radix__pte_update " Aneesh Kumar K.V
2016-11-28 6:17 ` [PATCH v7 7/7] powerpc/mm: Batch tlb flush when invalidating pte entries Aneesh Kumar K.V
2016-11-29 11:32 ` [PATCH v7 0/7] Radix pte update tlbflush optimizations Balbir Singh
2016-11-30 4:30 ` Michael Ellerman
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