From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from gate.crashing.org (gate.crashing.org [63.228.1.57]) (using TLSv1 with cipher DHE-RSA-AES256-SHA (256/256 bits)) (No client certificate requested) by lists.ozlabs.org (Postfix) with ESMTPS id 3tdVQQ5v2jzDvMX for ; Wed, 14 Dec 2016 06:39:26 +1100 (AEDT) Date: Tue, 13 Dec 2016 13:15:14 -0600 From: Segher Boessenkool To: Christophe Leroy Cc: Benjamin Herrenschmidt , Paul Mackerras , Michael Ellerman , Scott Wood , Peter Zijlstra , Ingo Molnar , Arnaldo Carvalho de Melo , Alexander Shishkin , linuxppc-dev@lists.ozlabs.org, linux-kernel@vger.kernel.org Subject: Re: [RFC 1/2] powerpc/32: Unset MSR RI in exception epilogs Message-ID: <20161213191514.GJ30845@gate.crashing.org> References: Mime-Version: 1.0 Content-Type: text/plain; charset=us-ascii In-Reply-To: List-Id: Linux on PowerPC Developers Mail List List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , On Tue, Dec 13, 2016 at 07:19:41PM +0100, Christophe Leroy wrote: > At exception prologs, once SRR0 and SRR1 have been saved, MSR RI is > set to mark the interrupt as recoverable. > > MSR RI has to be unset before writing into SRR0 and SRR1 at exception > epilogs. Why? What goes wrong without this? Etc. Segher