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From: Benjamin Herrenschmidt <benh@kernel.crashing.org>
To: linuxppc-dev@lists.ozlabs.org
Cc: Steven Munroe <munroesj@linux.vnet.ibm.com>,
	Benjamin Herrenschmidt <benh@kernel.crashing.org>
Subject: [PATCH 7/9] powerpc/64: Add L2 and L3 cache shape info
Date: Sun,  8 Jan 2017 17:31:48 -0600	[thread overview]
Message-ID: <20170108233150.15353-7-benh@kernel.crashing.org> (raw)
In-Reply-To: <20170108233150.15353-1-benh@kernel.crashing.org>

Retrieved from device-tree when available

Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
---
 arch/powerpc/include/asm/cache.h |  2 ++
 arch/powerpc/kernel/setup_64.c   | 25 ++++++++++++++++++++-----
 2 files changed, 22 insertions(+), 5 deletions(-)

diff --git a/arch/powerpc/include/asm/cache.h b/arch/powerpc/include/asm/cache.h
index ceb7376..3987bd9 100644
--- a/arch/powerpc/include/asm/cache.h
+++ b/arch/powerpc/include/asm/cache.h
@@ -40,6 +40,8 @@ struct ppc_cache_info {
 struct ppc64_caches {
 	struct ppc_cache_info l1d;
 	struct ppc_cache_info l1i;
+	struct ppc_cache_info l2;
+	struct ppc_cache_info l3;
 };
 
 extern struct ppc64_caches ppc64_caches;
diff --git a/arch/powerpc/kernel/setup_64.c b/arch/powerpc/kernel/setup_64.c
index e2946a7..216e305 100644
--- a/arch/powerpc/kernel/setup_64.c
+++ b/arch/powerpc/kernel/setup_64.c
@@ -457,22 +457,37 @@ static bool __init parse_cache_info(struct device_node *np,
 
 void __init initialize_cache_info(void)
 {
-	struct device_node *np;
+	struct device_node *cpu, *l2, *l3 = NULL;
 
 	DBG(" -> initialize_cache_info()\n");
 
-	np  = of_find_node_by_type(NULL, "cpu");
+	cpu = of_find_node_by_type(NULL, "cpu");
 
 	/*
 	 * We're assuming *all* of the CPUs have the same
 	 * d-cache and i-cache sizes... -Peter
 	 */
-	if (np) {
-		if (!parse_cache_info(np, false, &ppc64_caches.l1d))
+	if (cpu) {
+		if (!parse_cache_info(cpu, false, &ppc64_caches.l1d))
 			DBG("Argh, can't find dcache properties !\n");
 
-		if (!parse_cache_info(np, true, &ppc64_caches.l1i))
+		if (!parse_cache_info(cpu, true, &ppc64_caches.l1i))
 			DBG("Argh, can't find icache properties !\n");
+
+		/* Try to find the L2 and L3 if any. Assume they are
+		 * unified and use the D-side properties
+		 */
+		l2 = of_find_next_cache_node(cpu);
+		of_node_put(cpu);
+		if (l2) {
+			parse_cache_info(l2, false, &ppc64_caches.l2);
+			l3 = of_find_next_cache_node(l2);
+			of_node_put(l2);
+		}
+		if (l3) {
+			parse_cache_info(l3, false, &ppc64_caches.l3);
+			of_node_put(l3);
+		}
 	}
 
 	/* For use by binfmt_elf */
-- 
2.9.3

  parent reply	other threads:[~2017-01-08 23:32 UTC|newest]

Thread overview: 14+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2017-01-08 23:31 [PATCH 1/9] powerpc: Move ARCH_DLINFO out of uapi Benjamin Herrenschmidt
2017-01-08 23:31 ` [PATCH 2/9] powerpc: Move {d, i, u}cache_bsize definitions to a common place Benjamin Herrenschmidt
2017-01-08 23:31 ` [PATCH 3/9] powerpc: Remove obsolete comment about patching instructions Benjamin Herrenschmidt
2017-01-08 23:31 ` [PATCH 4/9] powerpc/64: Fix naming of cache block vs. cache line Benjamin Herrenschmidt
2017-01-08 23:31 ` [PATCH 5/9] powerpc/64: Retrieve number of L1 cache sets from device-tree Benjamin Herrenschmidt
2017-01-08 23:31 ` [PATCH 6/9] powerpc/64: Clean up ppc64_caches using a struct per cache Benjamin Herrenschmidt
2017-01-08 23:31 ` Benjamin Herrenschmidt [this message]
2017-01-08 23:31 ` [PATCH 8/9] powerpc/64: Hard code cache geometry on POWER8 Benjamin Herrenschmidt
2017-01-08 23:31 ` [PATCH 9/9] powerpc: A new cache geometry aux vectors Benjamin Herrenschmidt
2017-01-10 16:16   ` Paul Clarke
2017-01-10 16:26     ` Benjamin Herrenschmidt
2017-01-30 20:27   ` Michael Ellerman
2017-01-30 20:35     ` Benjamin Herrenschmidt
  -- strict thread matches above, loose matches on Subject: below --
2017-01-04  5:15 [PATCH 1/9] powerpc: Move ARCH_DLINFO out of uapi Benjamin Herrenschmidt
2017-01-04  5:15 ` [PATCH 7/9] powerpc/64: Add L2 and L3 cache shape info Benjamin Herrenschmidt

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