[RFC[PATCH 0/4] POWER9 machine check handler

[RFC[PATCH 0/4] POWER9 machine check handler

[Nicholas Piggin]

So far I've only got this tested in mambo simulator, but
some recoverable and unrecoverable events seem to work.

Thanks,
Nick

Nicholas Piggin (4):
  powerpc: machine check allow handler to set severity and initiator
  powerpc/powernv: machine check rework recovery flushing
  powerpc/powernv: cope with non-synchronous machine checks
  powerpc/powernv: handle POWER9 machine checks

 arch/powerpc/include/asm/bitops.h     |   4 +
 arch/powerpc/include/asm/mce.h        | 108 +++++++++++-
 arch/powerpc/kernel/cputable.c        |   3 +
 arch/powerpc/kernel/mce.c             |  90 +++++++++-
 arch/powerpc/kernel/mce_power.c       | 324 +++++++++++++++++++++++++++-------
 arch/powerpc/platforms/powernv/opal.c |  19 +-
 6 files changed, 465 insertions(+), 83 deletions(-)

-- 
2.11.0

[PATCH 1/4] powerpc: machine check allow handler to set severity and initiator

[Nicholas Piggin]

Currently these are hardcoded values.

mce_error_info should not have to be versioned because it's only used
for passing data from within the MCE subsystem.

Signed-off-by: Nicholas Piggin <npiggin@gmail.com>
---
 arch/powerpc/include/asm/mce.h  | 3 ++-
 arch/powerpc/kernel/mce.c       | 7 ++++---
 arch/powerpc/kernel/mce_power.c | 6 ++++++
 3 files changed, 12 insertions(+), 4 deletions(-)

diff --git a/arch/powerpc/include/asm/mce.h b/arch/powerpc/include/asm/mce.h
index f97d8cb6bdf6..b2a5865ccd87 100644
--- a/arch/powerpc/include/asm/mce.h
+++ b/arch/powerpc/include/asm/mce.h
@@ -177,7 +177,8 @@ struct mce_error_info {
 		enum MCE_EratErrorType erat_error_type:8;
 		enum MCE_TlbErrorType tlb_error_type:8;
 	} u;
-	uint8_t		reserved[2];
+	enum MCE_Severity	severity:8;
+	enum MCE_Initiator	initiator:8;
 };
 
 #define MAX_MC_EVT	100
diff --git a/arch/powerpc/kernel/mce.c b/arch/powerpc/kernel/mce.c
index c6923ff45131..d7a88dce67e8 100644
--- a/arch/powerpc/kernel/mce.c
+++ b/arch/powerpc/kernel/mce.c
@@ -90,13 +90,14 @@ void save_mce_event(struct pt_regs *regs, long handled,
 	mce->gpr3 = regs->gpr[3];
 	mce->in_use = 1;
 
-	mce->initiator = MCE_INITIATOR_CPU;
 	/* Mark it recovered if we have handled it and MSR(RI=1). */
 	if (handled && (regs->msr & MSR_RI))
 		mce->disposition = MCE_DISPOSITION_RECOVERED;
 	else
 		mce->disposition = MCE_DISPOSITION_NOT_RECOVERED;
-	mce->severity = MCE_SEV_ERROR_SYNC;
+
+	mce->initiator = mce_err->initiator;
+	mce->severity = mce_err->severity;
 
 	/*
 	 * Populate the mce error_type and type-specific error_type.
@@ -268,7 +269,7 @@ void machine_check_print_event_info(struct machine_check_event *evt)
 
 	printk("%s%s Machine check interrupt [%s]\n", level, sevstr,
 	       evt->disposition == MCE_DISPOSITION_RECOVERED ?
-	       "Recovered" : "[Not recovered");
+	       "Recovered" : "Not recovered");
 	printk("%s  Initiator: %s\n", level,
 	       evt->initiator == MCE_INITIATOR_CPU ? "CPU" : "Unknown");
 	switch (evt->error_type) {
diff --git a/arch/powerpc/kernel/mce_power.c b/arch/powerpc/kernel/mce_power.c
index 7353991c4ece..c37fc5fdd433 100644
--- a/arch/powerpc/kernel/mce_power.c
+++ b/arch/powerpc/kernel/mce_power.c
@@ -281,6 +281,9 @@ long __machine_check_early_realmode_p7(struct pt_regs *regs)
 	long handled = 1;
 	struct mce_error_info mce_error_info = { 0 };
 
+	mce_error_info.severity = MCE_SEV_ERROR_SYNC;
+	mce_error_info.initiator = MCE_INITIATOR_CPU;
+
 	srr1 = regs->msr;
 	nip = regs->nip;
 
@@ -352,6 +355,9 @@ long __machine_check_early_realmode_p8(struct pt_regs *regs)
 	long handled = 1;
 	struct mce_error_info mce_error_info = { 0 };
 
+	mce_error_info.severity = MCE_SEV_ERROR_SYNC;
+	mce_error_info.initiator = MCE_INITIATOR_CPU;
+
 	srr1 = regs->msr;
 	nip = regs->nip;
 
-- 
2.11.0

[PATCH 2/4] powerpc/powernv: machine check rework recovery flushing

[Nicholas Piggin]

Put the ifdefs into a flush handler call, and have callers ask for
particular type of flushes. Also add an ERAT flush.

Signed-off-by: Nicholas Piggin <npiggin@gmail.com>
---
 arch/powerpc/kernel/mce_power.c | 124 +++++++++++++++++++---------------------
 1 file changed, 59 insertions(+), 65 deletions(-)

diff --git a/arch/powerpc/kernel/mce_power.c b/arch/powerpc/kernel/mce_power.c
index c37fc5fdd433..79a7488593fa 100644
--- a/arch/powerpc/kernel/mce_power.c
+++ b/arch/powerpc/kernel/mce_power.c
@@ -114,83 +114,74 @@ static void flush_and_reload_slb(void)
 		asm volatile("slbmte %0,%1" : : "r" (rs), "r" (rb));
 	}
 }
-#endif
 
-static long mce_handle_derror(uint64_t dsisr, uint64_t slb_error_bits)
+static void flush_erat(void)
 {
-	long handled = 1;
+	asm volatile(PPC_INVALIDATE_ERAT : : :"memory");
+}
+#endif
 
-	/*
-	 * flush and reload SLBs for SLB errors and flush TLBs for TLB errors.
-	 * reset the error bits whenever we handle them so that at the end
-	 * we can check whether we handled all of them or not.
-	 * */
+#define MCE_FLUSH_SLB 1
+#define MCE_FLUSH_TLB 1
+#define MCE_FLUSH_ERAT 1
+
+static int mce_flush(int what)
+{
 #ifdef CONFIG_PPC_STD_MMU_64
-	if (dsisr & slb_error_bits) {
+	if (what == MCE_FLUSH_SLB) {
 		flush_and_reload_slb();
-		/* reset error bits */
-		dsisr &= ~(slb_error_bits);
+		return 1;
 	}
-	if (dsisr & P7_DSISR_MC_TLB_MULTIHIT_MFTLB) {
-		if (cur_cpu_spec && cur_cpu_spec->flush_tlb)
-			cur_cpu_spec->flush_tlb(TLB_INVAL_SCOPE_GLOBAL);
-		/* reset error bits */
-		dsisr &= ~P7_DSISR_MC_TLB_MULTIHIT_MFTLB;
+	if (what == MCE_FLUSH_ERAT) {
+		flush_erat();
+		return 1;
 	}
 #endif
-	/* Any other errors we don't understand? */
-	if (dsisr & 0xffffffffUL)
-		handled = 0;
+	if (what == MCE_FLUSH_TLB) {
+		if (cur_cpu_spec && cur_cpu_spec->flush_tlb) {
+			cur_cpu_spec->flush_tlb(TLB_INVAL_SCOPE_GLOBAL);
+			return 1;
+		}
+	}
 
-	return handled;
+	return 0;
 }
 
-static long mce_handle_derror_p7(uint64_t dsisr)
+static int mce_handle_flush_derrors(uint64_t dsisr, uint64_t slb, uint64_t tlb, uint64_t erat)
 {
-	return mce_handle_derror(dsisr, P7_DSISR_MC_SLB_ERRORS);
+	if ((dsisr & slb) && mce_flush(MCE_FLUSH_SLB))
+		dsisr &= ~slb;
+	if ((dsisr & erat) && mce_flush(MCE_FLUSH_ERAT))
+		dsisr &= ~erat;
+	if ((dsisr & tlb) && mce_flush(MCE_FLUSH_TLB))
+		dsisr &= ~tlb;
+	/* Any other errors we don't understand? */
+	if (dsisr)
+		return 0;
+	return 1;
 }
 
-static long mce_handle_common_ierror(uint64_t srr1)
+static long mce_handle_derror_p7(uint64_t dsisr)
 {
-	long handled = 0;
+	return mce_handle_flush_derrors(dsisr,
+			P7_DSISR_MC_SLB_ERRORS,
+			P7_DSISR_MC_TLB_MULTIHIT_MFTLB,
+			0);
+}
 
+static long mce_handle_ierror_p7(uint64_t srr1)
+{
 	switch (P7_SRR1_MC_IFETCH(srr1)) {
-	case 0:
-		break;
-#ifdef CONFIG_PPC_STD_MMU_64
 	case P7_SRR1_MC_IFETCH_SLB_PARITY:
 	case P7_SRR1_MC_IFETCH_SLB_MULTIHIT:
-		/* flush and reload SLBs for SLB errors. */
-		flush_and_reload_slb();
-		handled = 1;
-		break;
+	case P7_SRR1_MC_IFETCH_SLB_BOTH:
+		return mce_flush(MCE_FLUSH_SLB);
+
 	case P7_SRR1_MC_IFETCH_TLB_MULTIHIT:
-		if (cur_cpu_spec && cur_cpu_spec->flush_tlb) {
-			cur_cpu_spec->flush_tlb(TLB_INVAL_SCOPE_GLOBAL);
-			handled = 1;
-		}
-		break;
-#endif
+		return mce_flush(MCE_FLUSH_TLB);
 	default:
-		break;
-	}
-
-	return handled;
-}
-
-static long mce_handle_ierror_p7(uint64_t srr1)
-{
-	long handled = 0;
-
-	handled = mce_handle_common_ierror(srr1);
-
-#ifdef CONFIG_PPC_STD_MMU_64
-	if (P7_SRR1_MC_IFETCH(srr1) == P7_SRR1_MC_IFETCH_SLB_BOTH) {
-		flush_and_reload_slb();
-		handled = 1;
+		return 0;
 	}
-#endif
-	return handled;
 }
 
 static void mce_get_common_ierror(struct mce_error_info *mce_err, uint64_t srr1)
@@ -331,22 +322,25 @@ static void mce_get_derror_p8(struct mce_error_info *mce_err, uint64_t dsisr)
 
 static long mce_handle_ierror_p8(uint64_t srr1)
 {
-	long handled = 0;
-
-	handled = mce_handle_common_ierror(srr1);
+	switch (P7_SRR1_MC_IFETCH(srr1)) {
+	case P7_SRR1_MC_IFETCH_SLB_PARITY:
+	case P7_SRR1_MC_IFETCH_SLB_MULTIHIT:
+	case P8_SRR1_MC_IFETCH_ERAT_MULTIHIT:
+		return mce_flush(MCE_FLUSH_SLB);
 
-#ifdef CONFIG_PPC_STD_MMU_64
-	if (P7_SRR1_MC_IFETCH(srr1) == P8_SRR1_MC_IFETCH_ERAT_MULTIHIT) {
-		flush_and_reload_slb();
-		handled = 1;
+	case P7_SRR1_MC_IFETCH_TLB_MULTIHIT:
+		return mce_flush(MCE_FLUSH_TLB);
+	default:
+		return 0;
 	}
-#endif
-	return handled;
 }
 
 static long mce_handle_derror_p8(uint64_t dsisr)
 {
-	return mce_handle_derror(dsisr, P8_DSISR_MC_SLB_ERRORS);
+	return mce_handle_flush_derrors(dsisr,
+			P8_DSISR_MC_SLB_ERRORS,
+			P7_DSISR_MC_TLB_MULTIHIT_MFTLB,
+			0);
 }
 
 long __machine_check_early_realmode_p8(struct pt_regs *regs)
-- 
2.11.0

[PATCH 3/4] powerpc/powernv: cope with non-synchronous machine checks

[Nicholas Piggin]

Asynchronous machine checks don't correspond to the instruction or
even task that is currently running. Therefore only synchronous
machine checks should attempt to kill the currently running task
to recover.

Signed-off-by: Nicholas Piggin <npiggin@gmail.com>
---
 arch/powerpc/platforms/powernv/opal.c | 19 +++++--------------
 1 file changed, 5 insertions(+), 14 deletions(-)

diff --git a/arch/powerpc/platforms/powernv/opal.c b/arch/powerpc/platforms/powernv/opal.c
index 282293572dc8..8cd1656f0535 100644
--- a/arch/powerpc/platforms/powernv/opal.c
+++ b/arch/powerpc/platforms/powernv/opal.c
@@ -404,26 +404,17 @@ static int opal_recover_mce(struct pt_regs *regs,
 	} else if (evt->disposition == MCE_DISPOSITION_RECOVERED) {
 		/* Platform corrected itself */
 		recovered = 1;
-	} else if (ea && !is_kernel_addr(ea)) {
+	} else if (evt->severity == MCE_SEV_FATAL) {
+		/* Async or otherwise fatal machine check */
+		pr_err("Machine check interrupt unrecoverable\n");
+		recovered = 0;
+	} else if (user_mode(regs) && !is_global_init(current)) {
 		/*
-		 * Faulting address is not in kernel text. We should be fine.
-		 * We need to find which process uses this address.
 		 * For now, kill the task if we have received exception when
 		 * in userspace.
 		 *
 		 * TODO: Queue up this address for hwpoisioning later.
 		 */
-		if (user_mode(regs) && !is_global_init(current)) {
-			_exception(SIGBUS, regs, BUS_MCEERR_AR, regs->nip);
-			recovered = 1;
-		} else
-			recovered = 0;
-	} else if (user_mode(regs) && !is_global_init(current) &&
-		evt->severity == MCE_SEV_ERROR_SYNC) {
-		/*
-		 * If we have received a synchronous error when in userspace
-		 * kill the task.
-		 */
 		_exception(SIGBUS, regs, BUS_MCEERR_AR, regs->nip);
 		recovered = 1;
 	}
-- 
2.11.0

Re: [PATCH 3/4] powerpc/powernv: cope with non-synchronous machine checks

[kbuild test robot]

[-- Attachment #1: Type: text/plain, Size: 2297 bytes --]

Hi Nicholas,

[auto build test ERROR on powerpc/next]
[also build test ERROR on v4.10-rc8 next-20170216]
[if your patch is applied to the wrong git tree, please drop us a note to help improve the system]

url:    https://github.com/0day-ci/linux/commits/Nicholas-Piggin/POWER9-machine-check-handler/20170217-023423
base:   https://git.kernel.org/pub/scm/linux/kernel/git/powerpc/linux.git next
config: powerpc-defconfig (attached as .config)
compiler: powerpc64-linux-gnu-gcc (Debian 6.1.1-9) 6.1.1 20160705
reproduce:
        wget https://git.kernel.org/cgit/linux/kernel/git/wfg/lkp-tests.git/plain/sbin/make.cross -O ~/bin/make.cross
        chmod +x ~/bin/make.cross
        # save the attached .config to linux build tree
        make.cross ARCH=powerpc 

All errors (new ones prefixed by >>):

   arch/powerpc/platforms/powernv/opal.c: In function 'opal_recover_mce':
>> arch/powerpc/platforms/powernv/opal.c:398:11: error: unused variable 'ea' [-Werror=unused-variable]
     uint64_t ea = get_mce_fault_addr(evt);
              ^~
   cc1: all warnings being treated as errors

vim +/ea +398 arch/powerpc/platforms/powernv/opal.c

14a43e69 Benjamin Herrenschmidt 2011-09-19  392  }
14a43e69 Benjamin Herrenschmidt 2011-09-19  393  
b63a0ffe Mahesh Salgaonkar      2013-10-30  394  static int opal_recover_mce(struct pt_regs *regs,
b63a0ffe Mahesh Salgaonkar      2013-10-30  395  					struct machine_check_event *evt)
b63a0ffe Mahesh Salgaonkar      2013-10-30  396  {
b63a0ffe Mahesh Salgaonkar      2013-10-30  397  	int recovered = 0;
b63a0ffe Mahesh Salgaonkar      2013-10-30 @398  	uint64_t ea = get_mce_fault_addr(evt);
b63a0ffe Mahesh Salgaonkar      2013-10-30  399  
b63a0ffe Mahesh Salgaonkar      2013-10-30  400  	if (!(regs->msr & MSR_RI)) {
b63a0ffe Mahesh Salgaonkar      2013-10-30  401  		/* If MSR_RI isn't set, we cannot recover */

:::::: The code at line 398 was first introduced by commit
:::::: b63a0ffe35de7e5f9b907bbc2c783e702f7e15af powerpc/powernv: Machine check exception handling.

:::::: TO: Mahesh Salgaonkar <mahesh@linux.vnet.ibm.com>
:::::: CC: Benjamin Herrenschmidt <benh@kernel.crashing.org>

---
0-DAY kernel test infrastructure                Open Source Technology Center
https://lists.01.org/pipermail/kbuild-all                   Intel Corporation

[-- Attachment #2: .config.gz --]
[-- Type: application/gzip, Size: 22864 bytes --]

[PATCH 4/4] powerpc/powernv: handle POWER9 machine checks

[Nicholas Piggin]

This creates several new error types, and includes non-synchronous
exceptions. I don't know if that affects the API beyond there being
some unknown types in older code.

Some exceptions seem to be initiated by nest or remote/fabric, but
reporting of these is not implemented yet.

I started with mostly new values and functions rather than replicate
P7/8, because it was getting precarious with some values changing meaning.
It will need to all be converted into a table/data driven approach soon.
But for now it works.

Tested by manually constructing errors in simulator, so who knows if it
works on real hardware.

Signed-off-by: Nicholas Piggin <npiggin@gmail.com>
---
 arch/powerpc/include/asm/bitops.h |   4 +
 arch/powerpc/include/asm/mce.h    | 105 +++++++++++++++++++++
 arch/powerpc/kernel/cputable.c    |   3 +
 arch/powerpc/kernel/mce.c         |  83 ++++++++++++++++
 arch/powerpc/kernel/mce_power.c   | 194 ++++++++++++++++++++++++++++++++++++++
 5 files changed, 389 insertions(+)

diff --git a/arch/powerpc/include/asm/bitops.h b/arch/powerpc/include/asm/bitops.h
index 59abc620f8e8..5f057c74bf21 100644
--- a/arch/powerpc/include/asm/bitops.h
+++ b/arch/powerpc/include/asm/bitops.h
@@ -51,6 +51,10 @@
 #define PPC_BIT(bit)		(1UL << PPC_BITLSHIFT(bit))
 #define PPC_BITMASK(bs, be)	((PPC_BIT(bs) - PPC_BIT(be)) | PPC_BIT(bs))
 
+/* Put a PPC bit into a "normal" bit position */
+#define PPC_BITEXTRACT(bits, ppc_bit, dst_bit)			\
+	((((bits) >> PPC_BITLSHIFT(ppc_bit)) & 1) << (dst_bit))
+
 #include <asm/barrier.h>
 
 /* Macro for generating the ***_bits() functions */
diff --git a/arch/powerpc/include/asm/mce.h b/arch/powerpc/include/asm/mce.h
index b2a5865ccd87..ed62efe01e49 100644
--- a/arch/powerpc/include/asm/mce.h
+++ b/arch/powerpc/include/asm/mce.h
@@ -66,6 +66,55 @@
 
 #define P8_DSISR_MC_SLB_ERRORS		(P7_DSISR_MC_SLB_ERRORS | \
 					 P8_DSISR_MC_ERAT_MULTIHIT_SEC)
+
+/*
+ * Machine Check bits on power9
+ */
+#define P9_SRR1_MC_LOADSTORE(srr1)	(((srr1) >> PPC_BITLSHIFT(42)) & 1)
+
+#define P9_SRR1_MC_IFETCH(srr1)	(	\
+	PPC_BITEXTRACT(srr1, 45, 0) |	\
+	PPC_BITEXTRACT(srr1, 44, 1) |	\
+	PPC_BITEXTRACT(srr1, 43, 2) |	\
+	PPC_BITEXTRACT(srr1, 36, 3) )
+
+/* 0 is reserved */
+#define P9_SRR1_MC_IFETCH_UE				1
+#define P9_SRR1_MC_IFETCH_SLB_PARITY			2
+#define P9_SRR1_MC_IFETCH_SLB_MULTIHIT			3
+#define P9_SRR1_MC_IFETCH_ERAT_MULTIHIT			4
+#define P9_SRR1_MC_IFETCH_TLB_MULTIHIT			5
+#define P9_SRR1_MC_IFETCH_UE_TLB_RELOAD			6
+/* 7 is reserved */
+#define P9_SRR1_MC_IFETCH_LINK_TIMEOUT			8
+#define P9_SRR1_MC_IFETCH_LINK_TABLEWALK_TIMEOUT	9
+/* 10 ? */
+#define P9_SRR1_MC_IFETCH_RA			11
+#define P9_SRR1_MC_IFETCH_RA_TABLEWALK		12
+#define P9_SRR1_MC_IFETCH_RA_ASYNC_STORE		13
+#define P9_SRR1_MC_IFETCH_LINK_ASYNC_STORE_TIMEOUT	14
+#define P9_SRR1_MC_IFETCH_RA_TABLEWALK_FOREIGN	15
+
+/* DSISR bits for machine check (On Power9) */
+#define P9_DSISR_MC_UE					(PPC_BIT(48))
+#define P9_DSISR_MC_UE_TABLEWALK			(PPC_BIT(49))
+#define P9_DSISR_MC_LINK_LOAD_TIMEOUT			(PPC_BIT(50))
+#define P9_DSISR_MC_LINK_TABLEWALK_TIMEOUT		(PPC_BIT(51))
+#define P9_DSISR_MC_ERAT_MULTIHIT			(PPC_BIT(52))
+#define P9_DSISR_MC_TLB_MULTIHIT_MFTLB			(PPC_BIT(53))
+#define P9_DSISR_MC_USER_TLBIE				(PPC_BIT(54))
+#define P9_DSISR_MC_SLB_PARITY_MFSLB			(PPC_BIT(55))
+#define P9_DSISR_MC_SLB_MULTIHIT_MFSLB			(PPC_BIT(56))
+#define P9_DSISR_MC_RA_LOAD				(PPC_BIT(57))
+#define P9_DSISR_MC_RA_TABLEWALK			(PPC_BIT(58))
+#define P9_DSISR_MC_RA_TABLEWALK_FOREIGN		(PPC_BIT(59))
+#define P9_DSISR_MC_RA_FOREIGN				(PPC_BIT(60))
+
+/* SLB error bits */
+#define P9_DSISR_MC_SLB_ERRORS		(P9_DSISR_MC_ERAT_MULTIHIT | \
+					 P9_DSISR_MC_SLB_PARITY_MFSLB | \
+					 P9_DSISR_MC_SLB_MULTIHIT_MFSLB)
+
 enum MCE_Version {
 	MCE_V1 = 1,
 };
@@ -93,6 +142,9 @@ enum MCE_ErrorType {
 	MCE_ERROR_TYPE_SLB = 2,
 	MCE_ERROR_TYPE_ERAT = 3,
 	MCE_ERROR_TYPE_TLB = 4,
+	MCE_ERROR_TYPE_USER = 5,
+	MCE_ERROR_TYPE_RA = 6,
+	MCE_ERROR_TYPE_LINK = 7,
 };
 
 enum MCE_UeErrorType {
@@ -121,6 +173,32 @@ enum MCE_TlbErrorType {
 	MCE_TLB_ERROR_MULTIHIT = 2,
 };
 
+enum MCE_UserErrorType {
+	MCE_USER_ERROR_INDETERMINATE = 0,
+	MCE_USER_ERROR_TLBIE = 1,
+};
+
+enum MCE_RaErrorType {
+	MCE_RA_ERROR_INDETERMINATE = 0,
+	MCE_RA_ERROR_IFETCH = 1,
+	MCE_RA_ERROR_PAGE_TABLE_WALK_IFETCH = 2,
+	MCE_RA_ERROR_PAGE_TABLE_WALK_IFETCH_FOREIGN = 3,
+	MCE_RA_ERROR_LOAD = 4,
+	MCE_RA_ERROR_STORE = 5,
+	MCE_RA_ERROR_PAGE_TABLE_WALK_LOAD_STORE = 6,
+	MCE_RA_ERROR_PAGE_TABLE_WALK_LOAD_STORE_FOREIGN = 7,
+	MCE_RA_ERROR_LOAD_STORE_FOREIGN = 8,
+};
+
+enum MCE_LinkErrorType {
+	MCE_LINK_ERROR_INDETERMINATE = 0,
+	MCE_LINK_ERROR_IFETCH_TIMEOUT = 1,
+	MCE_LINK_ERROR_PAGE_TABLE_WALK_IFETCH_TIMEOUT = 2,
+	MCE_LINK_ERROR_LOAD_TIMEOUT = 3,
+	MCE_LINK_ERROR_STORE_TIMEOUT = 4,
+	MCE_LINK_ERROR_PAGE_TABLE_WALK_LOAD_STORE_TIMEOUT = 5,
+};
+
 struct machine_check_event {
 	enum MCE_Version	version:8;	/* 0x00 */
 	uint8_t			in_use;		/* 0x01 */
@@ -166,6 +244,30 @@ struct machine_check_event {
 			uint64_t	effective_address;
 			uint8_t		reserved_2[16];
 		} tlb_error;
+
+		struct {
+			enum MCE_UserErrorType user_error_type:8;
+			uint8_t		effective_address_provided;
+			uint8_t		reserved_1[6];
+			uint64_t	effective_address;
+			uint8_t		reserved_2[16];
+		} user_error;
+
+		struct {
+			enum MCE_RaErrorType ra_error_type:8;
+			uint8_t		effective_address_provided;
+			uint8_t		reserved_1[6];
+			uint64_t	effective_address;
+			uint8_t		reserved_2[16];
+		} ra_error;
+
+		struct {
+			enum MCE_LinkErrorType link_error_type:8;
+			uint8_t		effective_address_provided;
+			uint8_t		reserved_1[6];
+			uint64_t	effective_address;
+			uint8_t		reserved_2[16];
+		} link_error;
 	} u;
 };
 
@@ -176,6 +278,9 @@ struct mce_error_info {
 		enum MCE_SlbErrorType slb_error_type:8;
 		enum MCE_EratErrorType erat_error_type:8;
 		enum MCE_TlbErrorType tlb_error_type:8;
+		enum MCE_UserErrorType user_error_type:8;
+		enum MCE_RaErrorType ra_error_type:8;
+		enum MCE_LinkErrorType link_error_type:8;
 	} u;
 	enum MCE_Severity	severity:8;
 	enum MCE_Initiator	initiator:8;
diff --git a/arch/powerpc/kernel/cputable.c b/arch/powerpc/kernel/cputable.c
index 6a82ef039c50..5feefdacaea8 100644
--- a/arch/powerpc/kernel/cputable.c
+++ b/arch/powerpc/kernel/cputable.c
@@ -77,6 +77,7 @@ extern void __flush_tlb_power8(unsigned int action);
 extern void __flush_tlb_power9(unsigned int action);
 extern long __machine_check_early_realmode_p7(struct pt_regs *regs);
 extern long __machine_check_early_realmode_p8(struct pt_regs *regs);
+extern long __machine_check_early_realmode_p9(struct pt_regs *regs);
 #endif /* CONFIG_PPC64 */
 #if defined(CONFIG_E500)
 extern void __setup_cpu_e5500(unsigned long offset, struct cpu_spec* spec);
@@ -523,6 +524,7 @@ static struct cpu_spec __initdata cpu_specs[] = {
 		.cpu_setup		= __setup_cpu_power9,
 		.cpu_restore		= __restore_cpu_power9,
 		.flush_tlb		= __flush_tlb_power9,
+		.machine_check_early	= __machine_check_early_realmode_p9,
 		.platform		= "power9",
 	},
 	{	/* Power9 */
@@ -542,6 +544,7 @@ static struct cpu_spec __initdata cpu_specs[] = {
 		.cpu_setup		= __setup_cpu_power9,
 		.cpu_restore		= __restore_cpu_power9,
 		.flush_tlb		= __flush_tlb_power9,
+		.machine_check_early	= __machine_check_early_realmode_p9,
 		.platform		= "power9",
 	},
 	{	/* Cell Broadband Engine */
diff --git a/arch/powerpc/kernel/mce.c b/arch/powerpc/kernel/mce.c
index d7a88dce67e8..4348ed83b77c 100644
--- a/arch/powerpc/kernel/mce.c
+++ b/arch/powerpc/kernel/mce.c
@@ -58,6 +58,15 @@ static void mce_set_error_info(struct machine_check_event *mce,
 	case MCE_ERROR_TYPE_TLB:
 		mce->u.tlb_error.tlb_error_type = mce_err->u.tlb_error_type;
 		break;
+	case MCE_ERROR_TYPE_USER:
+		mce->u.user_error.user_error_type = mce_err->u.user_error_type;
+		break;
+	case MCE_ERROR_TYPE_RA:
+		mce->u.ra_error.ra_error_type = mce_err->u.ra_error_type;
+		break;
+	case MCE_ERROR_TYPE_LINK:
+		mce->u.link_error.link_error_type = mce_err->u.link_error_type;
+		break;
 	case MCE_ERROR_TYPE_UNKNOWN:
 	default:
 		break;
@@ -116,6 +125,15 @@ void save_mce_event(struct pt_regs *regs, long handled,
 	} else if (mce->error_type == MCE_ERROR_TYPE_ERAT) {
 		mce->u.erat_error.effective_address_provided = true;
 		mce->u.erat_error.effective_address = addr;
+	} else if (mce->error_type == MCE_ERROR_TYPE_USER) {
+		mce->u.user_error.effective_address_provided = true;
+		mce->u.user_error.effective_address = addr;
+	} else if (mce->error_type == MCE_ERROR_TYPE_RA) {
+		mce->u.ra_error.effective_address_provided = true;
+		mce->u.ra_error.effective_address = addr;
+	} else if (mce->error_type == MCE_ERROR_TYPE_LINK) {
+		mce->u.link_error.effective_address_provided = true;
+		mce->u.link_error.effective_address = addr;
 	} else if (mce->error_type == MCE_ERROR_TYPE_UE) {
 		mce->u.ue_error.effective_address_provided = true;
 		mce->u.ue_error.effective_address = addr;
@@ -240,6 +258,29 @@ void machine_check_print_event_info(struct machine_check_event *evt)
 		"Parity",
 		"Multihit",
 	};
+	static const char *mc_user_types[] = {
+		"Indeterminate",
+		"tlbie(l) invalid",
+	};
+	static const char *mc_ra_types[] = {
+		"Indeterminate",
+		"Instruction fetch (bad)",
+		"Page table walk ifetch (bad)",
+		"Page table walk ifetch (foreign)",
+		"Load (bad)",
+		"Store (bad)",
+		"Page table walk Load/Store (bad)",
+		"Page table walk Load/Store (foreign)",
+		"Load/Store (foreign)",
+	};
+	static const char *mc_link_types[] = {
+		"Indeterminate",
+		"Instruction fetch (timeout)",
+		"Page table walk ifetch (timeout)",
+		"Load (timeout)",
+		"Store (timeout)",
+		"Page table walk Load/Store (timeout)",
+	};
 
 	/* Print things out */
 	if (evt->version != MCE_V1) {
@@ -316,6 +357,36 @@ void machine_check_print_event_info(struct machine_check_event *evt)
 			printk("%s    Effective address: %016llx\n",
 			       level, evt->u.tlb_error.effective_address);
 		break;
+	case MCE_ERROR_TYPE_USER:
+		subtype = evt->u.user_error.user_error_type <
+			ARRAY_SIZE(mc_user_types) ?
+			mc_user_types[evt->u.user_error.user_error_type]
+			: "Unknown";
+		printk("%s  Error type: User [%s]\n", level, subtype);
+		if (evt->u.user_error.effective_address_provided)
+			printk("%s    Effective address: %016llx\n",
+			       level, evt->u.user_error.effective_address);
+		break;
+	case MCE_ERROR_TYPE_RA:
+		subtype = evt->u.ra_error.ra_error_type <
+			ARRAY_SIZE(mc_ra_types) ?
+			mc_ra_types[evt->u.ra_error.ra_error_type]
+			: "Unknown";
+		printk("%s  Error type: Real address [%s]\n", level, subtype);
+		if (evt->u.ra_error.effective_address_provided)
+			printk("%s    Effective address: %016llx\n",
+			       level, evt->u.ra_error.effective_address);
+		break;
+	case MCE_ERROR_TYPE_LINK:
+		subtype = evt->u.link_error.link_error_type <
+			ARRAY_SIZE(mc_link_types) ?
+			mc_link_types[evt->u.link_error.link_error_type]
+			: "Unknown";
+		printk("%s  Error type: Link [%s]\n", level, subtype);
+		if (evt->u.link_error.effective_address_provided)
+			printk("%s    Effective address: %016llx\n",
+			       level, evt->u.link_error.effective_address);
+		break;
 	default:
 	case MCE_ERROR_TYPE_UNKNOWN:
 		printk("%s  Error type: Unknown\n", level);
@@ -342,6 +413,18 @@ uint64_t get_mce_fault_addr(struct machine_check_event *evt)
 		if (evt->u.tlb_error.effective_address_provided)
 			return evt->u.tlb_error.effective_address;
 		break;
+	case MCE_ERROR_TYPE_USER:
+		if (evt->u.user_error.effective_address_provided)
+			return evt->u.user_error.effective_address;
+		break;
+	case MCE_ERROR_TYPE_RA:
+		if (evt->u.ra_error.effective_address_provided)
+			return evt->u.ra_error.effective_address;
+		break;
+	case MCE_ERROR_TYPE_LINK:
+		if (evt->u.link_error.effective_address_provided)
+			return evt->u.link_error.effective_address;
+		break;
 	default:
 	case MCE_ERROR_TYPE_UNKNOWN:
 		break;
diff --git a/arch/powerpc/kernel/mce_power.c b/arch/powerpc/kernel/mce_power.c
index 79a7488593fa..54497d6dc76b 100644
--- a/arch/powerpc/kernel/mce_power.c
+++ b/arch/powerpc/kernel/mce_power.c
@@ -372,3 +372,197 @@ long __machine_check_early_realmode_p8(struct pt_regs *regs)
 	save_mce_event(regs, handled, &mce_error_info, nip, addr);
 	return handled;
 }
+
+static int mce_handle_derror_p9(struct pt_regs *regs, uint64_t *addr,
+		enum MCE_Severity *severity, enum MCE_Initiator *initiator)
+{
+	uint64_t dsisr = regs->dsisr;
+
+#if 0
+	/* Could invalidate all tlbs then step over failing tlbie(l)? */
+	if (dsisr & P9_DSISR_MC_USER_TLBIE) {
+		regs->nip += 4;
+		dsisr &= ~P9_DSISR_MC_USER_TLBIE;
+	}
+#endif
+
+	return mce_handle_flush_derrors(dsisr,
+			P9_DSISR_MC_SLB_PARITY_MFSLB |
+			P9_DSISR_MC_SLB_MULTIHIT_MFSLB,
+
+			P9_DSISR_MC_TLB_MULTIHIT_MFTLB,
+
+			P9_DSISR_MC_ERAT_MULTIHIT);
+}
+
+static int mce_handle_ierror_p9(struct pt_regs *regs, uint64_t *addr,
+		enum MCE_Severity *severity, enum MCE_Initiator *initiator)
+{
+	uint64_t srr1 = regs->msr;
+
+	switch (P9_SRR1_MC_IFETCH(srr1)) {
+	case P9_SRR1_MC_IFETCH_SLB_PARITY:
+	case P9_SRR1_MC_IFETCH_SLB_MULTIHIT:
+		return mce_flush(MCE_FLUSH_SLB);
+	case P9_SRR1_MC_IFETCH_TLB_MULTIHIT:
+		return mce_flush(MCE_FLUSH_TLB);
+	case P9_SRR1_MC_IFETCH_ERAT_MULTIHIT:
+		return mce_flush(MCE_FLUSH_ERAT);
+	default:
+		return 0;
+	}
+}
+
+static void mce_get_derror_p9(struct mce_error_info *mce_err,
+				uint64_t *addr, uint64_t dsisr)
+{
+	mce_err->severity = MCE_SEV_ERROR_SYNC;
+	mce_err->initiator = MCE_INITIATOR_CPU;
+
+	if (dsisr & P9_DSISR_MC_USER_TLBIE)
+		*addr = regs->nip;
+	else
+		*addr = regs->dar;
+
+	if (dsisr & P9_DSISR_MC_UE) {
+		mce_err->error_type = MCE_ERROR_TYPE_UE;
+		mce_err->u.ue_error_type = MCE_UE_ERROR_LOAD_STORE;
+	} else if (dsisr & P9_DSISR_MC_UE_TABLEWALK) {
+		mce_err->error_type = MCE_ERROR_TYPE_UE;
+		mce_err->u.ue_error_type = MCE_UE_ERROR_PAGE_TABLE_WALK_LOAD_STORE;
+	} else if (dsisr & P9_DSISR_MC_LINK_LOAD_TIMEOUT) {
+		mce_err->error_type = MCE_ERROR_TYPE_LINK;
+		mce_err->u.link_error_type = MCE_LINK_ERROR_LOAD_TIMEOUT;
+	} else if (dsisr & P9_DSISR_MC_LINK_TABLEWALK_TIMEOUT) {
+		mce_err->error_type = MCE_ERROR_TYPE_LINK;
+		mce_err->u.link_error_type = MCE_LINK_ERROR_PAGE_TABLE_WALK_LOAD_STORE_TIMEOUT;
+	} else if (dsisr & P9_DSISR_MC_ERAT_MULTIHIT) {
+		mce_err->error_type = MCE_ERROR_TYPE_ERAT;
+		mce_err->u.erat_error_type = MCE_ERAT_ERROR_MULTIHIT;
+	} else if (dsisr & P9_DSISR_MC_TLB_MULTIHIT_MFTLB) {
+		mce_err->error_type = MCE_ERROR_TYPE_TLB;
+		mce_err->u.tlb_error_type = MCE_TLB_ERROR_MULTIHIT;
+	} else if (dsisr & P9_DSISR_MC_USER_TLBIE) {
+		mce_err->error_type = MCE_ERROR_TYPE_USER;
+		mce_err->u.user_error_type = MCE_USER_ERROR_TLBIE;
+	} else if (dsisr & P9_DSISR_MC_SLB_PARITY_MFSLB) {
+		mce_err->error_type = MCE_ERROR_TYPE_SLB;
+		mce_err->u.slb_error_type = MCE_SLB_ERROR_PARITY;
+	} else if (dsisr & P9_DSISR_MC_SLB_MULTIHIT_MFSLB) {
+		mce_err->error_type = MCE_ERROR_TYPE_SLB;
+		mce_err->u.slb_error_type = MCE_SLB_ERROR_MULTIHIT;
+	} else if (dsisr & P9_DSISR_MC_RA_LOAD) {
+		mce_err->error_type = MCE_ERROR_TYPE_RA;
+		mce_err->u.ra_error_type = MCE_RA_ERROR_LOAD;
+	} else if (dsisr & P9_DSISR_MC_RA_TABLEWALK) {
+		mce_err->error_type = MCE_ERROR_TYPE_RA;
+		mce_err->u.ra_error_type = MCE_RA_ERROR_PAGE_TABLE_WALK_LOAD_STORE;
+	} else if (dsisr & P9_DSISR_MC_RA_TABLEWALK_FOREIGN) {
+		mce_err->error_type = MCE_ERROR_TYPE_RA;
+		mce_err->u.ra_error_type = MCE_RA_ERROR_PAGE_TABLE_WALK_LOAD_STORE_FOREIGN;
+	} else if (dsisr & P9_DSISR_MC_RA_FOREIGN) {
+		mce_err->error_type = MCE_ERROR_TYPE_RA;
+		mce_err->u.ra_error_type = MCE_RA_ERROR_LOAD_STORE_FOREIGN;
+	}
+}
+
+static void mce_get_ierror_p9(struct mce_error_info *mce_err,
+				uint64_t *addr, uint64_t srr1)
+{
+	switch (P9_SRR1_MC_IFETCH(srr1)) {
+	case P9_SRR1_MC_IFETCH_RA_ASYNC_STORE:
+	case P9_SRR1_MC_IFETCH_LINK_ASYNC_STORE_TIMEOUT:
+		mce_err->severity = MCE_SEV_FATAL;
+		break;
+	default:
+		mce_err->severity = MCE_SEV_ERROR_SYNC;
+		break;
+	}
+
+	mce_err->initiator = MCE_INITIATOR_CPU;
+
+	*addr = regs->nip;
+
+	switch (P9_SRR1_MC_IFETCH(srr1)) {
+	case P9_SRR1_MC_IFETCH_UE:
+		mce_err->error_type = MCE_ERROR_TYPE_UE;
+		mce_err->u.ue_error_type = MCE_UE_ERROR_IFETCH;
+		break;
+	case P9_SRR1_MC_IFETCH_SLB_PARITY:
+		mce_err->error_type = MCE_ERROR_TYPE_SLB;
+		mce_err->u.slb_error_type = MCE_SLB_ERROR_PARITY;
+		break;
+	case P9_SRR1_MC_IFETCH_SLB_MULTIHIT:
+		mce_err->error_type = MCE_ERROR_TYPE_SLB;
+		mce_err->u.slb_error_type = MCE_SLB_ERROR_MULTIHIT;
+		break;
+	case P9_SRR1_MC_IFETCH_ERAT_MULTIHIT:
+		mce_err->error_type = MCE_ERROR_TYPE_ERAT;
+		mce_err->u.erat_error_type = MCE_ERAT_ERROR_MULTIHIT;
+		break;
+	case P9_SRR1_MC_IFETCH_TLB_MULTIHIT:
+		mce_err->error_type = MCE_ERROR_TYPE_TLB;
+		mce_err->u.tlb_error_type = MCE_TLB_ERROR_MULTIHIT;
+		break;
+	case P9_SRR1_MC_IFETCH_UE_TLB_RELOAD:
+		mce_err->error_type = MCE_ERROR_TYPE_UE;
+		mce_err->u.ue_error_type = MCE_UE_ERROR_PAGE_TABLE_WALK_IFETCH;
+		break;
+	case P9_SRR1_MC_IFETCH_LINK_TIMEOUT:
+		mce_err->error_type = MCE_ERROR_TYPE_LINK;
+		mce_err->u.link_error_type = MCE_LINK_ERROR_IFETCH_TIMEOUT;
+		break;
+	case P9_SRR1_MC_IFETCH_LINK_TABLEWALK_TIMEOUT:
+		mce_err->error_type = MCE_ERROR_TYPE_LINK;
+		mce_err->u.link_error_type = MCE_LINK_ERROR_PAGE_TABLE_WALK_IFETCH_TIMEOUT;
+		break;
+	case P9_SRR1_MC_IFETCH_RA:
+		mce_err->error_type = MCE_ERROR_TYPE_RA;
+		mce_err->u.ra_error_type = MCE_RA_ERROR_IFETCH;
+		break;
+	case P9_SRR1_MC_IFETCH_RA_TABLEWALK:
+		mce_err->error_type = MCE_ERROR_TYPE_RA;
+		mce_err->u.ra_error_type = MCE_RA_ERROR_PAGE_TABLE_WALK_IFETCH;
+		break;
+	case P9_SRR1_MC_IFETCH_RA_ASYNC_STORE:
+		mce_err->error_type = MCE_ERROR_TYPE_RA;
+		mce_err->u.ra_error_type = MCE_RA_ERROR_STORE;
+		break;
+	case P9_SRR1_MC_IFETCH_LINK_ASYNC_STORE_TIMEOUT:
+		mce_err->error_type = MCE_ERROR_TYPE_LINK;
+		mce_err->u.link_error_type = MCE_LINK_ERROR_STORE_TIMEOUT;
+		break;
+	case P9_SRR1_MC_IFETCH_RA_TABLEWALK_FOREIGN:
+		mce_err->error_type = MCE_ERROR_TYPE_RA;
+		mce_err->u.ra_error_type = MCE_RA_ERROR_PAGE_TABLE_WALK_IFETCH_FOREIGN;
+		break;
+	default:
+		break;
+	}
+}
+
+long __machine_check_early_realmode_p9(struct pt_regs *regs)
+{
+	uint64_t nip, addr;
+	long handled;
+	struct mce_error_info mce_error_info = { 0 };
+	enum MCE_Severity severity = MCE_SEV_ERROR_SYNC;
+	enum MCE_Initiator initiator = MCE_INITIATOR_CPU;
+
+	nip = regs->nip;
+
+	if (P9_SRR1_MC_LOADSTORE(regs->msr)) {
+		handled = mce_handle_derror_p9(regs);
+		mce_get_derror_p9(&mce_error_info, &addr, regs->dsisr);
+	} else {
+		handled = mce_handle_ierror_p9(regs);
+		mce_get_ierror_p9(&mce_error_info, &addr, regs->msr);
+	}
+
+	/* Handle UE error. */
+	if (mce_error_info.error_type == MCE_ERROR_TYPE_UE)
+		handled = mce_handle_ue_error(regs);
+
+	save_mce_event(regs, handled, &mce_error_info, nip, addr);
+	return handled;
+}
-- 
2.11.0

Re: [PATCH 4/4] powerpc/powernv: handle POWER9 machine checks

[kbuild test robot]

[-- Attachment #1: Type: text/plain, Size: 8904 bytes --]

Hi Nicholas,

[auto build test ERROR on powerpc/next]
[also build test ERROR on v4.10-rc8 next-20170216]
[if your patch is applied to the wrong git tree, please drop us a note to help improve the system]

url:    https://github.com/0day-ci/linux/commits/Nicholas-Piggin/POWER9-machine-check-handler/20170217-023423
base:   https://git.kernel.org/pub/scm/linux/kernel/git/powerpc/linux.git next
config: powerpc-allyesconfig (attached as .config)
compiler: powerpc64-linux-gnu-gcc (Debian 6.1.1-9) 6.1.1 20160705
reproduce:
        wget https://git.kernel.org/cgit/linux/kernel/git/wfg/lkp-tests.git/plain/sbin/make.cross -O ~/bin/make.cross
        chmod +x ~/bin/make.cross
        # save the attached .config to linux build tree
        make.cross ARCH=powerpc 

All errors (new ones prefixed by >>):

   arch/powerpc/kernel/mce_power.c: In function 'mce_get_derror_p9':
>> arch/powerpc/kernel/mce_power.c:423:11: error: 'regs' undeclared (first use in this function)
      *addr = regs->nip;
              ^~~~
   arch/powerpc/kernel/mce_power.c:423:11: note: each undeclared identifier is reported only once for each function it appears in
   arch/powerpc/kernel/mce_power.c: In function 'mce_get_ierror_p9':
   arch/powerpc/kernel/mce_power.c:484:10: error: 'regs' undeclared (first use in this function)
     *addr = regs->nip;
             ^~~~
   arch/powerpc/kernel/mce_power.c: In function '__machine_check_early_realmode_p9':
>> arch/powerpc/kernel/mce_power.c:555:13: error: too few arguments to function 'mce_handle_derror_p9'
      handled = mce_handle_derror_p9(regs);
                ^~~~~~~~~~~~~~~~~~~~
   arch/powerpc/kernel/mce_power.c:376:12: note: declared here
    static int mce_handle_derror_p9(struct pt_regs *regs, uint64_t *addr,
               ^~~~~~~~~~~~~~~~~~~~
>> arch/powerpc/kernel/mce_power.c:558:13: error: too few arguments to function 'mce_handle_ierror_p9'
      handled = mce_handle_ierror_p9(regs);
                ^~~~~~~~~~~~~~~~~~~~
   arch/powerpc/kernel/mce_power.c:398:12: note: declared here
    static int mce_handle_ierror_p9(struct pt_regs *regs, uint64_t *addr,
               ^~~~~~~~~~~~~~~~~~~~
   arch/powerpc/kernel/mce_power.c:550:21: warning: unused variable 'initiator' [-Wunused-variable]
     enum MCE_Initiator initiator = MCE_INITIATOR_CPU;
                        ^~~~~~~~~
   arch/powerpc/kernel/mce_power.c:549:20: warning: unused variable 'severity' [-Wunused-variable]
     enum MCE_Severity severity = MCE_SEV_ERROR_SYNC;
                       ^~~~~~~~

vim +/regs +423 arch/powerpc/kernel/mce_power.c

   417					uint64_t *addr, uint64_t dsisr)
   418	{
   419		mce_err->severity = MCE_SEV_ERROR_SYNC;
   420		mce_err->initiator = MCE_INITIATOR_CPU;
   421	
   422		if (dsisr & P9_DSISR_MC_USER_TLBIE)
 > 423			*addr = regs->nip;
   424		else
   425			*addr = regs->dar;
   426	
   427		if (dsisr & P9_DSISR_MC_UE) {
   428			mce_err->error_type = MCE_ERROR_TYPE_UE;
   429			mce_err->u.ue_error_type = MCE_UE_ERROR_LOAD_STORE;
   430		} else if (dsisr & P9_DSISR_MC_UE_TABLEWALK) {
   431			mce_err->error_type = MCE_ERROR_TYPE_UE;
   432			mce_err->u.ue_error_type = MCE_UE_ERROR_PAGE_TABLE_WALK_LOAD_STORE;
   433		} else if (dsisr & P9_DSISR_MC_LINK_LOAD_TIMEOUT) {
   434			mce_err->error_type = MCE_ERROR_TYPE_LINK;
   435			mce_err->u.link_error_type = MCE_LINK_ERROR_LOAD_TIMEOUT;
   436		} else if (dsisr & P9_DSISR_MC_LINK_TABLEWALK_TIMEOUT) {
   437			mce_err->error_type = MCE_ERROR_TYPE_LINK;
   438			mce_err->u.link_error_type = MCE_LINK_ERROR_PAGE_TABLE_WALK_LOAD_STORE_TIMEOUT;
   439		} else if (dsisr & P9_DSISR_MC_ERAT_MULTIHIT) {
   440			mce_err->error_type = MCE_ERROR_TYPE_ERAT;
   441			mce_err->u.erat_error_type = MCE_ERAT_ERROR_MULTIHIT;
   442		} else if (dsisr & P9_DSISR_MC_TLB_MULTIHIT_MFTLB) {
   443			mce_err->error_type = MCE_ERROR_TYPE_TLB;
   444			mce_err->u.tlb_error_type = MCE_TLB_ERROR_MULTIHIT;
   445		} else if (dsisr & P9_DSISR_MC_USER_TLBIE) {
   446			mce_err->error_type = MCE_ERROR_TYPE_USER;
   447			mce_err->u.user_error_type = MCE_USER_ERROR_TLBIE;
   448		} else if (dsisr & P9_DSISR_MC_SLB_PARITY_MFSLB) {
   449			mce_err->error_type = MCE_ERROR_TYPE_SLB;
   450			mce_err->u.slb_error_type = MCE_SLB_ERROR_PARITY;
   451		} else if (dsisr & P9_DSISR_MC_SLB_MULTIHIT_MFSLB) {
   452			mce_err->error_type = MCE_ERROR_TYPE_SLB;
   453			mce_err->u.slb_error_type = MCE_SLB_ERROR_MULTIHIT;
   454		} else if (dsisr & P9_DSISR_MC_RA_LOAD) {
   455			mce_err->error_type = MCE_ERROR_TYPE_RA;
   456			mce_err->u.ra_error_type = MCE_RA_ERROR_LOAD;
   457		} else if (dsisr & P9_DSISR_MC_RA_TABLEWALK) {
   458			mce_err->error_type = MCE_ERROR_TYPE_RA;
   459			mce_err->u.ra_error_type = MCE_RA_ERROR_PAGE_TABLE_WALK_LOAD_STORE;
   460		} else if (dsisr & P9_DSISR_MC_RA_TABLEWALK_FOREIGN) {
   461			mce_err->error_type = MCE_ERROR_TYPE_RA;
   462			mce_err->u.ra_error_type = MCE_RA_ERROR_PAGE_TABLE_WALK_LOAD_STORE_FOREIGN;
   463		} else if (dsisr & P9_DSISR_MC_RA_FOREIGN) {
   464			mce_err->error_type = MCE_ERROR_TYPE_RA;
   465			mce_err->u.ra_error_type = MCE_RA_ERROR_LOAD_STORE_FOREIGN;
   466		}
   467	}
   468	
   469	static void mce_get_ierror_p9(struct mce_error_info *mce_err,
   470					uint64_t *addr, uint64_t srr1)
   471	{
   472		switch (P9_SRR1_MC_IFETCH(srr1)) {
   473		case P9_SRR1_MC_IFETCH_RA_ASYNC_STORE:
   474		case P9_SRR1_MC_IFETCH_LINK_ASYNC_STORE_TIMEOUT:
   475			mce_err->severity = MCE_SEV_FATAL;
   476			break;
   477		default:
   478			mce_err->severity = MCE_SEV_ERROR_SYNC;
   479			break;
   480		}
   481	
   482		mce_err->initiator = MCE_INITIATOR_CPU;
   483	
   484		*addr = regs->nip;
   485	
   486		switch (P9_SRR1_MC_IFETCH(srr1)) {
   487		case P9_SRR1_MC_IFETCH_UE:
   488			mce_err->error_type = MCE_ERROR_TYPE_UE;
   489			mce_err->u.ue_error_type = MCE_UE_ERROR_IFETCH;
   490			break;
   491		case P9_SRR1_MC_IFETCH_SLB_PARITY:
   492			mce_err->error_type = MCE_ERROR_TYPE_SLB;
   493			mce_err->u.slb_error_type = MCE_SLB_ERROR_PARITY;
   494			break;
   495		case P9_SRR1_MC_IFETCH_SLB_MULTIHIT:
   496			mce_err->error_type = MCE_ERROR_TYPE_SLB;
   497			mce_err->u.slb_error_type = MCE_SLB_ERROR_MULTIHIT;
   498			break;
   499		case P9_SRR1_MC_IFETCH_ERAT_MULTIHIT:
   500			mce_err->error_type = MCE_ERROR_TYPE_ERAT;
   501			mce_err->u.erat_error_type = MCE_ERAT_ERROR_MULTIHIT;
   502			break;
   503		case P9_SRR1_MC_IFETCH_TLB_MULTIHIT:
   504			mce_err->error_type = MCE_ERROR_TYPE_TLB;
   505			mce_err->u.tlb_error_type = MCE_TLB_ERROR_MULTIHIT;
   506			break;
   507		case P9_SRR1_MC_IFETCH_UE_TLB_RELOAD:
   508			mce_err->error_type = MCE_ERROR_TYPE_UE;
   509			mce_err->u.ue_error_type = MCE_UE_ERROR_PAGE_TABLE_WALK_IFETCH;
   510			break;
   511		case P9_SRR1_MC_IFETCH_LINK_TIMEOUT:
   512			mce_err->error_type = MCE_ERROR_TYPE_LINK;
   513			mce_err->u.link_error_type = MCE_LINK_ERROR_IFETCH_TIMEOUT;
   514			break;
   515		case P9_SRR1_MC_IFETCH_LINK_TABLEWALK_TIMEOUT:
   516			mce_err->error_type = MCE_ERROR_TYPE_LINK;
   517			mce_err->u.link_error_type = MCE_LINK_ERROR_PAGE_TABLE_WALK_IFETCH_TIMEOUT;
   518			break;
   519		case P9_SRR1_MC_IFETCH_RA:
   520			mce_err->error_type = MCE_ERROR_TYPE_RA;
   521			mce_err->u.ra_error_type = MCE_RA_ERROR_IFETCH;
   522			break;
   523		case P9_SRR1_MC_IFETCH_RA_TABLEWALK:
   524			mce_err->error_type = MCE_ERROR_TYPE_RA;
   525			mce_err->u.ra_error_type = MCE_RA_ERROR_PAGE_TABLE_WALK_IFETCH;
   526			break;
   527		case P9_SRR1_MC_IFETCH_RA_ASYNC_STORE:
   528			mce_err->error_type = MCE_ERROR_TYPE_RA;
   529			mce_err->u.ra_error_type = MCE_RA_ERROR_STORE;
   530			break;
   531		case P9_SRR1_MC_IFETCH_LINK_ASYNC_STORE_TIMEOUT:
   532			mce_err->error_type = MCE_ERROR_TYPE_LINK;
   533			mce_err->u.link_error_type = MCE_LINK_ERROR_STORE_TIMEOUT;
   534			break;
   535		case P9_SRR1_MC_IFETCH_RA_TABLEWALK_FOREIGN:
   536			mce_err->error_type = MCE_ERROR_TYPE_RA;
   537			mce_err->u.ra_error_type = MCE_RA_ERROR_PAGE_TABLE_WALK_IFETCH_FOREIGN;
   538			break;
   539		default:
   540			break;
   541		}
   542	}
   543	
   544	long __machine_check_early_realmode_p9(struct pt_regs *regs)
   545	{
   546		uint64_t nip, addr;
   547		long handled;
   548		struct mce_error_info mce_error_info = { 0 };
   549		enum MCE_Severity severity = MCE_SEV_ERROR_SYNC;
   550		enum MCE_Initiator initiator = MCE_INITIATOR_CPU;
   551	
   552		nip = regs->nip;
   553	
   554		if (P9_SRR1_MC_LOADSTORE(regs->msr)) {
 > 555			handled = mce_handle_derror_p9(regs);
   556			mce_get_derror_p9(&mce_error_info, &addr, regs->dsisr);
   557		} else {
 > 558			handled = mce_handle_ierror_p9(regs);
   559			mce_get_ierror_p9(&mce_error_info, &addr, regs->msr);
   560		}
   561	

---
0-DAY kernel test infrastructure                Open Source Technology Center
https://lists.01.org/pipermail/kbuild-all                   Intel Corporation

[-- Attachment #2: .config.gz --]
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Re: [PATCH 4/4] powerpc/powernv: handle POWER9 machine checks

[kbuild test robot]

[-- Attachment #1: Type: text/plain, Size: 10476 bytes --]

Hi Nicholas,

[auto build test ERROR on powerpc/next]
[also build test ERROR on v4.10-rc8 next-20170216]
[if your patch is applied to the wrong git tree, please drop us a note to help improve the system]

url:    https://github.com/0day-ci/linux/commits/Nicholas-Piggin/POWER9-machine-check-handler/20170217-023423
base:   https://git.kernel.org/pub/scm/linux/kernel/git/powerpc/linux.git next
config: powerpc-defconfig (attached as .config)
compiler: powerpc64-linux-gnu-gcc (Debian 6.1.1-9) 6.1.1 20160705
reproduce:
        wget https://git.kernel.org/cgit/linux/kernel/git/wfg/lkp-tests.git/plain/sbin/make.cross -O ~/bin/make.cross
        chmod +x ~/bin/make.cross
        # save the attached .config to linux build tree
        make.cross ARCH=powerpc 

All errors (new ones prefixed by >>):

   arch/powerpc/kernel/mce_power.c: In function 'mce_get_derror_p9':
   arch/powerpc/kernel/mce_power.c:423:11: error: 'regs' undeclared (first use in this function)
      *addr = regs->nip;
              ^~~~
   arch/powerpc/kernel/mce_power.c:423:11: note: each undeclared identifier is reported only once for each function it appears in
   arch/powerpc/kernel/mce_power.c: In function 'mce_get_ierror_p9':
   arch/powerpc/kernel/mce_power.c:484:10: error: 'regs' undeclared (first use in this function)
     *addr = regs->nip;
             ^~~~
   arch/powerpc/kernel/mce_power.c: In function '__machine_check_early_realmode_p9':
   arch/powerpc/kernel/mce_power.c:555:13: error: too few arguments to function 'mce_handle_derror_p9'
      handled = mce_handle_derror_p9(regs);
                ^~~~~~~~~~~~~~~~~~~~
   arch/powerpc/kernel/mce_power.c:376:12: note: declared here
    static int mce_handle_derror_p9(struct pt_regs *regs, uint64_t *addr,
               ^~~~~~~~~~~~~~~~~~~~
   arch/powerpc/kernel/mce_power.c:558:13: error: too few arguments to function 'mce_handle_ierror_p9'
      handled = mce_handle_ierror_p9(regs);
                ^~~~~~~~~~~~~~~~~~~~
   arch/powerpc/kernel/mce_power.c:398:12: note: declared here
    static int mce_handle_ierror_p9(struct pt_regs *regs, uint64_t *addr,
               ^~~~~~~~~~~~~~~~~~~~
>> arch/powerpc/kernel/mce_power.c:550:21: error: unused variable 'initiator' [-Werror=unused-variable]
     enum MCE_Initiator initiator = MCE_INITIATOR_CPU;
                        ^~~~~~~~~
>> arch/powerpc/kernel/mce_power.c:549:20: error: unused variable 'severity' [-Werror=unused-variable]
     enum MCE_Severity severity = MCE_SEV_ERROR_SYNC;
                       ^~~~~~~~
   cc1: all warnings being treated as errors

vim +/initiator +550 arch/powerpc/kernel/mce_power.c

   370			handled = mce_handle_ue_error(regs);
   371	
   372		save_mce_event(regs, handled, &mce_error_info, nip, addr);
   373		return handled;
   374	}
   375	
 > 376	static int mce_handle_derror_p9(struct pt_regs *regs, uint64_t *addr,
   377			enum MCE_Severity *severity, enum MCE_Initiator *initiator)
   378	{
   379		uint64_t dsisr = regs->dsisr;
   380	
   381	#if 0
   382		/* Could invalidate all tlbs then step over failing tlbie(l)? */
   383		if (dsisr & P9_DSISR_MC_USER_TLBIE) {
   384			regs->nip += 4;
   385			dsisr &= ~P9_DSISR_MC_USER_TLBIE;
   386		}
   387	#endif
   388	
   389		return mce_handle_flush_derrors(dsisr,
   390				P9_DSISR_MC_SLB_PARITY_MFSLB |
   391				P9_DSISR_MC_SLB_MULTIHIT_MFSLB,
   392	
   393				P9_DSISR_MC_TLB_MULTIHIT_MFTLB,
   394	
   395				P9_DSISR_MC_ERAT_MULTIHIT);
   396	}
   397	
   398	static int mce_handle_ierror_p9(struct pt_regs *regs, uint64_t *addr,
   399			enum MCE_Severity *severity, enum MCE_Initiator *initiator)
   400	{
   401		uint64_t srr1 = regs->msr;
   402	
   403		switch (P9_SRR1_MC_IFETCH(srr1)) {
   404		case P9_SRR1_MC_IFETCH_SLB_PARITY:
   405		case P9_SRR1_MC_IFETCH_SLB_MULTIHIT:
   406			return mce_flush(MCE_FLUSH_SLB);
   407		case P9_SRR1_MC_IFETCH_TLB_MULTIHIT:
   408			return mce_flush(MCE_FLUSH_TLB);
   409		case P9_SRR1_MC_IFETCH_ERAT_MULTIHIT:
   410			return mce_flush(MCE_FLUSH_ERAT);
   411		default:
   412			return 0;
   413		}
   414	}
   415	
   416	static void mce_get_derror_p9(struct mce_error_info *mce_err,
   417					uint64_t *addr, uint64_t dsisr)
   418	{
   419		mce_err->severity = MCE_SEV_ERROR_SYNC;
   420		mce_err->initiator = MCE_INITIATOR_CPU;
   421	
   422		if (dsisr & P9_DSISR_MC_USER_TLBIE)
   423			*addr = regs->nip;
   424		else
   425			*addr = regs->dar;
   426	
   427		if (dsisr & P9_DSISR_MC_UE) {
   428			mce_err->error_type = MCE_ERROR_TYPE_UE;
   429			mce_err->u.ue_error_type = MCE_UE_ERROR_LOAD_STORE;
   430		} else if (dsisr & P9_DSISR_MC_UE_TABLEWALK) {
   431			mce_err->error_type = MCE_ERROR_TYPE_UE;
   432			mce_err->u.ue_error_type = MCE_UE_ERROR_PAGE_TABLE_WALK_LOAD_STORE;
   433		} else if (dsisr & P9_DSISR_MC_LINK_LOAD_TIMEOUT) {
   434			mce_err->error_type = MCE_ERROR_TYPE_LINK;
   435			mce_err->u.link_error_type = MCE_LINK_ERROR_LOAD_TIMEOUT;
   436		} else if (dsisr & P9_DSISR_MC_LINK_TABLEWALK_TIMEOUT) {
   437			mce_err->error_type = MCE_ERROR_TYPE_LINK;
   438			mce_err->u.link_error_type = MCE_LINK_ERROR_PAGE_TABLE_WALK_LOAD_STORE_TIMEOUT;
   439		} else if (dsisr & P9_DSISR_MC_ERAT_MULTIHIT) {
   440			mce_err->error_type = MCE_ERROR_TYPE_ERAT;
   441			mce_err->u.erat_error_type = MCE_ERAT_ERROR_MULTIHIT;
   442		} else if (dsisr & P9_DSISR_MC_TLB_MULTIHIT_MFTLB) {
   443			mce_err->error_type = MCE_ERROR_TYPE_TLB;
   444			mce_err->u.tlb_error_type = MCE_TLB_ERROR_MULTIHIT;
   445		} else if (dsisr & P9_DSISR_MC_USER_TLBIE) {
   446			mce_err->error_type = MCE_ERROR_TYPE_USER;
   447			mce_err->u.user_error_type = MCE_USER_ERROR_TLBIE;
   448		} else if (dsisr & P9_DSISR_MC_SLB_PARITY_MFSLB) {
   449			mce_err->error_type = MCE_ERROR_TYPE_SLB;
   450			mce_err->u.slb_error_type = MCE_SLB_ERROR_PARITY;
   451		} else if (dsisr & P9_DSISR_MC_SLB_MULTIHIT_MFSLB) {
   452			mce_err->error_type = MCE_ERROR_TYPE_SLB;
   453			mce_err->u.slb_error_type = MCE_SLB_ERROR_MULTIHIT;
   454		} else if (dsisr & P9_DSISR_MC_RA_LOAD) {
   455			mce_err->error_type = MCE_ERROR_TYPE_RA;
   456			mce_err->u.ra_error_type = MCE_RA_ERROR_LOAD;
   457		} else if (dsisr & P9_DSISR_MC_RA_TABLEWALK) {
   458			mce_err->error_type = MCE_ERROR_TYPE_RA;
   459			mce_err->u.ra_error_type = MCE_RA_ERROR_PAGE_TABLE_WALK_LOAD_STORE;
   460		} else if (dsisr & P9_DSISR_MC_RA_TABLEWALK_FOREIGN) {
   461			mce_err->error_type = MCE_ERROR_TYPE_RA;
   462			mce_err->u.ra_error_type = MCE_RA_ERROR_PAGE_TABLE_WALK_LOAD_STORE_FOREIGN;
   463		} else if (dsisr & P9_DSISR_MC_RA_FOREIGN) {
   464			mce_err->error_type = MCE_ERROR_TYPE_RA;
   465			mce_err->u.ra_error_type = MCE_RA_ERROR_LOAD_STORE_FOREIGN;
   466		}
   467	}
   468	
   469	static void mce_get_ierror_p9(struct mce_error_info *mce_err,
   470					uint64_t *addr, uint64_t srr1)
   471	{
   472		switch (P9_SRR1_MC_IFETCH(srr1)) {
   473		case P9_SRR1_MC_IFETCH_RA_ASYNC_STORE:
   474		case P9_SRR1_MC_IFETCH_LINK_ASYNC_STORE_TIMEOUT:
   475			mce_err->severity = MCE_SEV_FATAL;
   476			break;
   477		default:
   478			mce_err->severity = MCE_SEV_ERROR_SYNC;
   479			break;
   480		}
   481	
   482		mce_err->initiator = MCE_INITIATOR_CPU;
   483	
   484		*addr = regs->nip;
   485	
   486		switch (P9_SRR1_MC_IFETCH(srr1)) {
   487		case P9_SRR1_MC_IFETCH_UE:
   488			mce_err->error_type = MCE_ERROR_TYPE_UE;
   489			mce_err->u.ue_error_type = MCE_UE_ERROR_IFETCH;
   490			break;
   491		case P9_SRR1_MC_IFETCH_SLB_PARITY:
   492			mce_err->error_type = MCE_ERROR_TYPE_SLB;
   493			mce_err->u.slb_error_type = MCE_SLB_ERROR_PARITY;
   494			break;
   495		case P9_SRR1_MC_IFETCH_SLB_MULTIHIT:
   496			mce_err->error_type = MCE_ERROR_TYPE_SLB;
   497			mce_err->u.slb_error_type = MCE_SLB_ERROR_MULTIHIT;
   498			break;
   499		case P9_SRR1_MC_IFETCH_ERAT_MULTIHIT:
   500			mce_err->error_type = MCE_ERROR_TYPE_ERAT;
   501			mce_err->u.erat_error_type = MCE_ERAT_ERROR_MULTIHIT;
   502			break;
   503		case P9_SRR1_MC_IFETCH_TLB_MULTIHIT:
   504			mce_err->error_type = MCE_ERROR_TYPE_TLB;
   505			mce_err->u.tlb_error_type = MCE_TLB_ERROR_MULTIHIT;
   506			break;
   507		case P9_SRR1_MC_IFETCH_UE_TLB_RELOAD:
   508			mce_err->error_type = MCE_ERROR_TYPE_UE;
   509			mce_err->u.ue_error_type = MCE_UE_ERROR_PAGE_TABLE_WALK_IFETCH;
   510			break;
   511		case P9_SRR1_MC_IFETCH_LINK_TIMEOUT:
   512			mce_err->error_type = MCE_ERROR_TYPE_LINK;
   513			mce_err->u.link_error_type = MCE_LINK_ERROR_IFETCH_TIMEOUT;
   514			break;
   515		case P9_SRR1_MC_IFETCH_LINK_TABLEWALK_TIMEOUT:
   516			mce_err->error_type = MCE_ERROR_TYPE_LINK;
   517			mce_err->u.link_error_type = MCE_LINK_ERROR_PAGE_TABLE_WALK_IFETCH_TIMEOUT;
   518			break;
   519		case P9_SRR1_MC_IFETCH_RA:
   520			mce_err->error_type = MCE_ERROR_TYPE_RA;
   521			mce_err->u.ra_error_type = MCE_RA_ERROR_IFETCH;
   522			break;
   523		case P9_SRR1_MC_IFETCH_RA_TABLEWALK:
   524			mce_err->error_type = MCE_ERROR_TYPE_RA;
   525			mce_err->u.ra_error_type = MCE_RA_ERROR_PAGE_TABLE_WALK_IFETCH;
   526			break;
   527		case P9_SRR1_MC_IFETCH_RA_ASYNC_STORE:
   528			mce_err->error_type = MCE_ERROR_TYPE_RA;
   529			mce_err->u.ra_error_type = MCE_RA_ERROR_STORE;
   530			break;
   531		case P9_SRR1_MC_IFETCH_LINK_ASYNC_STORE_TIMEOUT:
   532			mce_err->error_type = MCE_ERROR_TYPE_LINK;
   533			mce_err->u.link_error_type = MCE_LINK_ERROR_STORE_TIMEOUT;
   534			break;
   535		case P9_SRR1_MC_IFETCH_RA_TABLEWALK_FOREIGN:
   536			mce_err->error_type = MCE_ERROR_TYPE_RA;
   537			mce_err->u.ra_error_type = MCE_RA_ERROR_PAGE_TABLE_WALK_IFETCH_FOREIGN;
   538			break;
   539		default:
   540			break;
   541		}
   542	}
   543	
   544	long __machine_check_early_realmode_p9(struct pt_regs *regs)
   545	{
   546		uint64_t nip, addr;
   547		long handled;
   548		struct mce_error_info mce_error_info = { 0 };
 > 549		enum MCE_Severity severity = MCE_SEV_ERROR_SYNC;
 > 550		enum MCE_Initiator initiator = MCE_INITIATOR_CPU;
   551	
   552		nip = regs->nip;
   553	
   554		if (P9_SRR1_MC_LOADSTORE(regs->msr)) {
   555			handled = mce_handle_derror_p9(regs);
   556			mce_get_derror_p9(&mce_error_info, &addr, regs->dsisr);
   557		} else {
 > 558			handled = mce_handle_ierror_p9(regs);
   559			mce_get_ierror_p9(&mce_error_info, &addr, regs->msr);
   560		}
   561	

---
0-DAY kernel test infrastructure                Open Source Technology Center
https://lists.01.org/pipermail/kbuild-all                   Intel Corporation

[-- Attachment #2: .config.gz --]
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Re: [RFC[PATCH 0/4] POWER9 machine check handler

[Nicholas Piggin]

On Fri, 17 Feb 2017 03:01:10 +1000
Nicholas Piggin <npiggin@gmail.com> wrote:

> So far I've only got this tested in mambo simulator, but
> some recoverable and unrecoverable events seem to work.

Ugh, I forgot to update before sending sorry. It's just a
couple of small compiler bugs so I'll resend after getting
feedback first.

Thanks,
Nick