From: Nicholas Piggin <npiggin@gmail.com>
To: Mahesh Jagannath Salgaonkar <mahesh@linux.vnet.ibm.com>
Cc: linuxppc-dev@lists.ozlabs.org, Michael Ellerman <mpe@ellerman.id.au>
Subject: Re: [PATCH 3/3] powerpc/64s: POWER9 machine check handler
Date: Thu, 9 Mar 2017 15:35:15 +1000 [thread overview]
Message-ID: <20170309153515.07f3b255@roar.ozlabs.ibm.com> (raw)
In-Reply-To: <b9166ee8-faa3-41be-78ec-4968e0ee18b4@linux.vnet.ibm.com>
On Tue, 28 Feb 2017 12:37:23 +0530
Mahesh Jagannath Salgaonkar <mahesh@linux.vnet.ibm.com> wrote:
> On 02/28/2017 07:30 AM, Nicholas Piggin wrote:
> > +long __machine_check_early_realmode_p9(struct pt_regs *regs)
> > +{
> > + uint64_t nip, addr;
> > + long handled;
> > + struct mce_error_info mce_error_info = { 0 };
> > +
> > + nip = regs->nip;
> > +
> > + if (P9_SRR1_MC_LOADSTORE(regs->msr)) {
>
> Asynch store errors are reported in the srr1 with codes srr1 42=1, 36=1,
> 43=1 and 44:45 = 01 or 10. Since srr1 42=1, you may end up in
> mce_handle_derror_p9() for asynch errors and look for error bits in
> DSISR instead in SRR1. We will miss detecting asynch errors completely.
After clarification from hardware, Asynch MCEs are reported with
SRR1 bit 42 = 0, so I think this is okay.
Thanks,
Nick
prev parent reply other threads:[~2017-03-09 5:35 UTC|newest]
Thread overview: 9+ messages / expand[flat|nested] mbox.gz Atom feed top
2017-02-28 2:00 [PATCH 0/3 v2] MCE handler for POWER9 Nicholas Piggin
2017-02-28 2:00 ` [PATCH 1/3] powerpc/64s: fix handling of non-synchronous machine checks Nicholas Piggin
2017-02-28 5:57 ` Mahesh Jagannath Salgaonkar
2017-02-28 8:43 ` Nicholas Piggin
2017-03-14 11:45 ` [1/3] " Michael Ellerman
2017-02-28 2:00 ` [PATCH 2/3] powerpc/64s: allow machine check handler to set severity and initiator Nicholas Piggin
2017-02-28 2:00 ` [PATCH 3/3] powerpc/64s: POWER9 machine check handler Nicholas Piggin
2017-02-28 7:07 ` Mahesh Jagannath Salgaonkar
2017-03-09 5:35 ` Nicholas Piggin [this message]
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