From: Paul Mackerras <paulus@ozlabs.org>
To: "Aneesh Kumar K.V" <aneesh.kumar@linux.vnet.ibm.com>
Cc: benh@kernel.crashing.org, mpe@ellerman.id.au,
linuxppc-dev@lists.ozlabs.org
Subject: Re: [PATCH V2 09/11] powerpc/mm: Lower the max real address to 51 bits
Date: Fri, 17 Mar 2017 09:27:25 +1100 [thread overview]
Message-ID: <20170316222725.GI10100@fergus.ozlabs.ibm.com> (raw)
In-Reply-To: <1489660329-22501-10-git-send-email-aneesh.kumar@linux.vnet.ibm.com>
On Thu, Mar 16, 2017 at 04:02:07PM +0530, Aneesh Kumar K.V wrote:
> Max value supported by hardware is 51 bits address. Radix page table define
> a slot of 57 bits for future expansion. We restrict the value supported in
> linux kernel 51 bits, so that we can use the bits between 57-51 for storing
> hash linux page table bits. This is done in the next patch.
>
> This will free up the software page table bits to be used for features
> that are needed for both hash and radix. The current hash linux page table
> format doesn't have any free software bits. Moving hash linux page table
> specific bits to top of RPN field free up the software bits for other purpose.
>
> Signed-off-by: Aneesh Kumar K.V <aneesh.kumar@linux.vnet.ibm.com>
> ---
There are a couple of comment typos below, but for the actual code change:
Reviewed-by: Paul Mackerras <paulus@ozlabs.org>
> arch/powerpc/include/asm/book3s/64/pgtable.h | 24 ++++++++++++++++++++++--
> 1 file changed, 22 insertions(+), 2 deletions(-)
>
> diff --git a/arch/powerpc/include/asm/book3s/64/pgtable.h b/arch/powerpc/include/asm/book3s/64/pgtable.h
> index 96566df547a8..c470dcc815d5 100644
> --- a/arch/powerpc/include/asm/book3s/64/pgtable.h
> +++ b/arch/powerpc/include/asm/book3s/64/pgtable.h
> @@ -38,6 +38,25 @@
> #define _RPAGE_RSV4 0x0200000000000000UL
> #define _RPAGE_RPN0 0x01000
> #define _RPAGE_RPN1 0x02000
> +/* Max physicall address bit as per radix table */
physical not physicall
> +#define _RPAGE_PA_MAX 57
> +/*
> + * Max physical address bit we will use for now.
> + *
> + * This is mostly a hardware limitation and for now Power9 has
> + * a 51 bit limit.
> + *
> + * This is different from the number of physical bit required to address
> + * the last byte of memory. That is defined by MAX_PHYSMEM_BITS.
> + * MAX_PHYSMEM_BITS is a linux limitation imposed by the maximum
> + * number of sections we can support (SECTIONS_SHIFT).
> + *
> + * This is different from Radix page table limitation above and
> + * should always be less than that. The limit is done such that
> + * we can overload the bits between _RPAGE_PA_MAX and _PAGE_PA_MAX
> + * for hash linux page table specific bits.
> + */
> +#define _PAGE_PA_MAX 51
>
> #define _PAGE_SOFT_DIRTY _RPAGE_SW3 /* software: software dirty tracking */
> #define _PAGE_SPECIAL _RPAGE_SW2 /* software: special page */
> @@ -51,10 +70,11 @@
> */
> #define _PAGE_NO_CACHE _PAGE_TOLERANT
> /*
> - * We support 57 bit real address in pte. Clear everything above 57, and
> + * We support _RPAGE_PA_MAX bit real address in pte. On the linux side
> + * we are limited by _PAGE_PA_MAX. Clear everything above _PAGE_PA_MAX
> * every thing below PAGE_SHIFT;
You lost an "and" in that last sentence.
> */
> -#define PTE_RPN_MASK (((1UL << 57) - 1) & (PAGE_MASK))
> +#define PTE_RPN_MASK (((1UL << _PAGE_PA_MAX) - 1) & (PAGE_MASK))
> /*
> * set of bits not changed in pmd_modify. Even though we have hash specific bits
> * in here, on radix we expect them to be zero.
> --
> 2.7.4
Paul.
next prev parent reply other threads:[~2017-03-16 22:34 UTC|newest]
Thread overview: 28+ messages / expand[flat|nested] mbox.gz Atom feed top
2017-03-16 10:31 [PATCH V2 00/11] powerpc/mm/hash: Cleanup and fixes Aneesh Kumar K.V
2017-03-16 10:31 ` [PATCH V2 01/11] powerpc/mm/nohash: MM_SLICE is only used by book3s 64 Aneesh Kumar K.V
2017-03-16 22:00 ` Paul Mackerras
2017-03-16 10:32 ` [PATCH V2 02/11] powerpc/mm/slice: when computing slice mask limit lowe slice max addr correctly Aneesh Kumar K.V
2017-03-16 22:03 ` Paul Mackerras
2017-03-17 6:55 ` Aneesh Kumar K.V
2017-03-16 10:32 ` [PATCH V2 03/11] powerpc/mm: Cleanup bits definition between hash and radix Aneesh Kumar K.V
2017-03-16 22:16 ` Paul Mackerras
2017-03-16 10:32 ` [PATCH V2 04/11] powerpc/mm/radix: rename _PAGE_LARGE to R_PAGE_LARGE Aneesh Kumar K.V
2017-03-16 22:16 ` Paul Mackerras
2017-03-16 10:32 ` [PATCH V2 05/11] powerpc/mm: Add translation mode information in /proc/cpuinfo Aneesh Kumar K.V
2017-03-16 22:17 ` Paul Mackerras
2017-03-16 10:32 ` [PATCH V2 06/11] powerpc/mm/hugetlb: Filter out hugepage size not supported by page table layout Aneesh Kumar K.V
2017-03-16 22:19 ` Paul Mackerras
2017-03-16 10:32 ` [PATCH V2 07/11] powerpc/mm: Conditional defines of pte bits are messy Aneesh Kumar K.V
2017-03-16 22:21 ` Paul Mackerras
2017-03-16 10:32 ` [PATCH V2 08/11] powerpc/mm: Express everything based on Radix page table defines Aneesh Kumar K.V
2017-03-16 22:24 ` Paul Mackerras
2017-03-16 10:32 ` [PATCH V2 09/11] powerpc/mm: Lower the max real address to 51 bits Aneesh Kumar K.V
2017-03-16 21:26 ` Benjamin Herrenschmidt
2017-03-17 3:39 ` Aneesh Kumar K.V
2017-03-16 22:27 ` Paul Mackerras [this message]
2017-03-16 10:32 ` [PATCH V2 10/11] powerpc/mm/radix: Make max pfn bits a variable Aneesh Kumar K.V
2017-03-16 22:29 ` Paul Mackerras
2017-03-17 8:54 ` Aneesh Kumar K.V
2017-03-16 10:32 ` [PATCH V2 11/11] powerpc/mm: Move hash specific pte bits to be top bits of RPN Aneesh Kumar K.V
2017-03-16 22:34 ` Paul Mackerras
2017-03-17 3:37 ` Aneesh Kumar K.V
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