From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mail-pg0-x243.google.com (mail-pg0-x243.google.com [IPv6:2607:f8b0:400e:c05::243]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by lists.ozlabs.org (Postfix) with ESMTPS id 3vpF1H2dNQzDqC4 for ; Thu, 23 Mar 2017 03:06:43 +1100 (AEDT) Received: by mail-pg0-x243.google.com with SMTP id w20so6368340pgc.1 for ; Wed, 22 Mar 2017 09:06:43 -0700 (PDT) Date: Thu, 23 Mar 2017 02:06:28 +1000 From: Nicholas Piggin To: "Gautham R. Shenoy" Cc: Michael Ellerman , Michael Neuling , Benjamin Herrenschmidt , "Shreyas B. Prabhu" , Shilpasri G Bhat , Vaidyanathan Srinivasan , Anton Blanchard , Balbir Singh , Akshay Adiga , Mahesh J Salgaonkar , linuxppc-dev@lists.ozlabs.org, linux-kernel@vger.kernel.org Subject: Re: [v3 PATCH 4/4] powernv: Recover correct PACA on wakeup from a stop on P9 DD1 Message-ID: <20170323020628.56b40eed@roar.ozlabs.ibm.com> In-Reply-To: <2387240280c6445bd22ee9be621997b6f951ef3d.1490194710.git.ego@linux.vnet.ibm.com> References: <2387240280c6445bd22ee9be621997b6f951ef3d.1490194710.git.ego@linux.vnet.ibm.com> MIME-Version: 1.0 Content-Type: text/plain; charset=US-ASCII List-Id: Linux on PowerPC Developers Mail List List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , On Wed, 22 Mar 2017 20:34:17 +0530 "Gautham R. Shenoy" wrote: > From: "Gautham R. Shenoy" > > POWER9 DD1.0 hardware has an issue due to which the SPRs of a thread > waking up from stop 0,1,2 with ESL=1 can endup being misplaced in the > core. Thus the HSPRG0 of a thread waking up from can contain the paca > pointer of its sibling. > > This patch implements a context recovery framework within threads of a > core, by provisioning space in paca_struct for saving every sibling > threads's paca pointers. Basically, we should be able to arrive at the > right paca pointer from any of the thread's existing paca pointer. > > At bootup, during powernv idle-init, we save the paca address of every > CPU in each one its siblings paca_struct in the slot corresponding to > this CPU's index in the core. > > On wakeup from a stop, the thread will determine its index in the core > from the TIR register and recover its PACA pointer by indexing into > the correct slot in the provisioned space in the current PACA. > > Furthermore, ensure that the NVGPRs are restored from the stack on the > way out by setting the NAPSTATELOST in paca. > > [Changelog written with inputs from svaidy@linux.vnet.ibm.com] Looks good. Reviewed-by: Nicholas Piggin